Patents by Inventor Hall E. Jarman

Hall E. Jarman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6111315
    Abstract: A semiconductor package includes a stiffener strip (10) having a die pad (18) and a body portion (12). A first surface (4) of the die pad (18) is offset from a second surface (3) of the body portion (12) a predetermined amount. The stiffener strip (10) includes an internal edge (27) concentrically disposed about the die pad (18) and tie straps (16) connecting the internal edge (27) to the die pad (18). A die (28) is affixed to the first surface (4) of the die pad (18). A substrate (20) has a first surface (17) and a second surface (19), with the second surface (19) being affixed to the first surface (2) of the body portion (12). The substrate (20) includes a window (22) and conductive elements (24). A plastic molding material (33) encompasses the die (28), at least a portion of the stiffener strip (10), and at least a portion of the substrate (20).
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: August 29, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: William P. Stearns, Hall E. Jarman, Nozar Hassanzadeh
  • Patent number: 4276460
    Abstract: A switch consisting of a housing and a spring is provided with convenient attachment means for assembly in combination with a printed circuit board. The spring functions as both an electrical connection means, and as a tension mechanism for biasing the assembly to compensate for tolerances.
    Type: Grant
    Filed: May 29, 1979
    Date of Patent: June 30, 1981
    Assignee: Texas Instruments Incorporated
    Inventors: Barry F. Haesly, Hall E. Jarman
  • Patent number: 3977071
    Abstract: A process for etching high depth-to-width ratio grooves in the surface of monocrystalline germanium-comprising semiconductor material by orienting the material so that the surface to be etched is parallel to a (110) plane of the crystal structure; orienting an etching mask on that surface such that the length of the groove to be etched is parallel to a (111) plane of the crystal which is normal to said surface; and subjecting the semiconductor material to a preferential etchant which attacks fastest in a [110] direction of a germanium crystal and slowest in a [111] direction.
    Type: Grant
    Filed: September 29, 1969
    Date of Patent: August 31, 1976
    Assignee: Texas Instruments Incorporated
    Inventor: Hall E. Jarman