Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

Abstract: Disclosed is a video acquisition method. The method includes acquiring at least two existing video segments selected by a user through a video selection interface, where the video selection interface is an interface which is switched from a video capture interface or a detail interface; and synthesizing the at least two existing video segments into a target video that has a duration less than or equal to a preset video duration based on the preset video duration. Further disclosed are a video acquisition device, a terminal and a storage medium.

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body, a second gate structure that extends over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer has a first section and a second section. The second semiconductor layer is positioned laterally between the first section of the first semiconductor layer and the second section of the first semiconductor layer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.