Abstract: An apparatus and method for managing a memory is disclosed. A discharging unit discharges overcharged bit lines in memory. The discharging unit discharges the bit lines after a predetermined time after the last memory access. The discharging unit also discharges the bit lines after a microprocessor comes out of a low power mode.

Abstract: An application specific integrated circuit is provided on a chip where a combinatorial logic circuitry such as a RAM memory array, logic circuitry and control circuitry may be operated in the normal mode with the addition of a built-in, self-test feature whereby the registers can be converted to multifunction shift registers which are connected in a serial fashion to form a shift chain snake through which data patterns can be shifted. Additionally, control circuitry is provided to select certain multifunction shift registers as test pattern generators and other multifunction shift registers are receivers of signatures which can be accessed by a maintenance controller to check proper operability of the system and its combinatorial logic.

Abstract: A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.

Abstract: A method for internal self-testing is provided for a VLSI chip having gates, logic, registers, memory circuitry, etc. The registers are connected into a shift chain circuit form. A set of control flip-flops operate to convert the registers to multifunction shift registers (MFSR's) which operate as flip-flops during a test cycle and as latches during normal operations. Selected MFSR's function to generate test patterns to the chip circuitry which have output signals to an output MFSR which collects a signature that can be compared to a predetermined signature to determine error-free or error-incurred operation of the VLSI circuitry.