Abstract: A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal.

Abstract: A memory includes a row decoder, column logic, and a memory array having a plurality of memory cells arranged in rows and columns. A plurality of write word lines are coupled to the row decoder. A plurality of complementary write word lines is coupled to the row decoder. A plurality of read bit lines is coupled to the column logic. A plurality of write bit lines is coupled to the column logic. A plurality of column decoded write enable lines is coupled to the column logic. Each memory cell of the plurality of memory cells is coupled to a corresponding write control circuit. Each write control circuit comprises a transmission gate coupled between a column decoded write enable line and an access transistor of a memory cell. The transmission gate is controlled by a write word line signal.

Abstract: A portion of a memory may include a first memory block, including a first memory cell coupled to a first memory data line, a second memory block, including a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.

Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.

Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Abstract: A portion of a memory may include a first memory block, comprising a first memory cell coupled to a first memory data line, a second memory block, comprising a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.

Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Abstract: A memory circuit includes a memory structure having sets of redundant columns where each set of redundant columns can replace a column of the memory array that may include a defective cell. Selection of the redundant columns for a memory access is accomplished by performing an address comparison between the address provided to the memory and one or more predetermined values that indicate which portion of the data array each set of redundant columns replaces. Based on this address comparison, a column redundancy select signal is asserted when a set of redundant columns is selected. For a read operation, the column redundancy select signal propagates through redundant column logic select the appropriate data from a particular set of redundant columns. This redundant data that is selected is substituted for data stored in the memory array for the read operation.

Abstract: A method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair; having a first match line and a first word line aligned along a second axis, the first match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the secon

Abstract: A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

Abstract: An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors of regular sense amplifiers (46) with a redundant multiplexer (83). When a redundant column is used to replace a defective regular column, a match circuit (88) generates a match signal for selecting a redundant multiplexer circuit (84, 85, or 86) and for deselecting a corresponding regular sense amplifier (46). The match circuit (88) includes emitter summing circuits (230, 240) to rapidly generate the match signal.

Abstract: A BICMOS level converter (60) for use at lower power supply voltages includes an input buffer (20) for receiving an ECL level input signal and providing level shifted buffered signals referenced to V.sub.SS, a differential amplifier (61), a clamping circuit (71 and 72) for preventing the bipolar transistors (64 and 65) from operating in saturation, cross-coupled pull-up circuit (67) for a stronger transition from a logic low to a logic high, and a cross-coupled half-latch (75) for reducing the power consumption. The BICMOS level converter (60) has improved switching speeds, wider margins, and reduced power consumption for use at 3.3 volts.

Abstract: A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced to a positive power supply voltage and provides buffered level shifted signals referenced to ground. The current sources (31 and 34) receive a power supply dependent bias voltage that changes in relation to a change in the positive power supply voltage. In turn, the voltage drop across the resistors (30 and 33) changes with respect to the positive power supply voltage such that the buffered level shifted signals are constant with respect to ground. The power supply dependent input buffer (20) is for use at low power supply voltages (such as 3.3 volts), resulting in low power consumption and wider margins on following stages, such as a level converter.

Abstract: A current driver circuit (10) sources current to an output node (N4) in response to an input signal (VI) being a logic high. The current driver circuit (10) utilizes a current source (16) which sinks current from the output node (N4) in response to the input signal (VI) switching from a logic high to a logic low. The current source (16) is deactivated for a predetermined time delay after the input signal (Vi) switches from a logic high to a logic low.