Abstract: A self adapting driver for controlling datapath hardware elements uses a generic driver and a configuration library to create a set of data structures and methods to map information provided by applications to physical tables. A set of virtual tables is implemented as an interface between the applications and the generic driver. The generic driver uses the configuration library to determine a mapping from the virtual tables to the physical tables. A virtual table schema definition is parsed to create the configuration library, such that changes to the physical infrastructure may be implemented as changes to the virtual table schema definition without adjusting the driver code. Thus automatically generated creation of generic packet forwarding drivers is able to be implemented through the use of a configuration language that defines the meaning of the information stored in the virtual tables.

Abstract: Service aware network devices coordinate function chains of virtual functions. The network devices are aware of which virtual functions exist and how to interconnect them in the most efficient manner and define and process service graphs that can be maintained, monitored and redirected. The network devices themselves implement and manage the service graphs, as opposed to the virtual servers that host the virtual functions.

Abstract: Each switch in a switch cluster is implemented as two logical switches—a logical UNI switch and a logical NNI switch implementing a Backbone Edge Bridge (BEB). The logical UNI switch handles forwarding to UNI receivers. The logical NNI switches are treated as independent switches by the SPB control plane and handle forwarding to NNI receivers. The two logical switches exchange packets through UNI/NNI and NNI/UNI translations (Mac-in-MAC encapsulation/decapsulation). The Inter-Switch Trunk is viewed as two logical channels—a UNI logical channel and an NNI logical channel. The logical UNI switch will forward packets having NNI receivers to the logical NNI switch. The logical NNI switch will forward packets having UNI receivers to the logical UNI switch only if the packet has a B-VID matching a B-VID assigned to the node of the switch cluster.

Abstract: Embodiments herein include systems and methods for providing a mechanism for efficient data synchronization of ARP records between two peer nodes of an SMLT system. Such techniques include modifying control information of ARP packets transmitted between peer nodes of the SMLT system to indicate originating SMLT ports. Techniques also include disabling MAC synchronization control messaging across the IST link. These techniques enable real-time synchronization ARP records for MAC learning without needing dedicated control messaging over the IST, thereby providing nodal and SMLT port failover and recovery.

Abstract: An operating system adds an application signature as a tag in a packet header. In one embodiment the tag is inserted as a Q-tag in an Ethernet header. When a network element receives the tagged packet, it uses the tag alone or in combination with one or more additional header fields to map the packet to a network virtualization identifier segregating the application traffic on the network. Services are applied to packets according to network virtualization identifier to enable distributed application of services without requiring network elements to maintain state associated with packet flows.

Abstract: Service aware network devices coordinate function chains of virtual functions. The network devices are aware of which virtual functions exist and how to interconnect them in the most efficient manner and define and process service graphs that can be maintained, monitored and redirected. The network devices themselves implement and manage the service graphs, as opposed to the virtual servers that host the virtual functions.

Abstract: A table based abstraction layer is interposed between applications and the packet forwarding hardware driver layer. All behavior and configuration of packet forwarding to be implemented in the hardware layer is articulated as fields in tables of the table based abstraction layer, and the higher level application software interacts with the hardware through the creation of and insertion and deletion of elements in these tables. The structure of the tables in the abstraction layer has no direct functional meaning to the hardware, but rather the tables of the table based abstraction layer simply exist to receive data to be inserted by the applications into the forwarding hardware. Information from the tables is extracted by the packet forwarding hardware driver layer and used to populate physical offset tables that may then be installed into the registers and physical tables utilized by the hardware to perform packet forwarding operations.

Abstract: Key lookup operations are broken into two instructions: a Key Dispatch Instruction (KDI), and a Return Result Instruction (RRI). The thread uses KDI to dispatch key information to a selected coprocessor to initiate a key lookup operation. Upon dispatch of the key value to the coprocessor, the KDI is retired to enable the thread to continue to dispatch and retire addition instructions in the pipeline and does not go idle. Subsequently, the thread will issue a RRI to obtain the key lookup result from the coprocessor. While a thread is executing, it maintains, as part of its context, a busy flag per coprocessor in a scoreboard register and a return result register per coprocessor. KDI causes the corresponding busy flag in the scoreboard register to be set. When the key lookup operation is complete, the busy flag is cleared and the result is stored in the return result register.

Abstract: A method, apparatus and computer program product for performing efficient loop instruction execution using bit vector scanning is presented. A bit vector is scanned, each bit in the bit vector representing at least one of a feature and a conditional status. The presence of a bit of said bit vector set to a first state is detected. The bit is set to a second state. An instruction address for a routine corresponding to said bit set to a first state is looked up using a bit position of said bit that was set to a first state. The routine is executed. The scanning, said detecting, said setting and said using are repeated until there are no remaining bits of said bit vector set to said first state.

Abstract: A method, apparatus and computer program product for providing Split Multi Link Trunk (SMLT) for Advanced Technology Attachment (ATA) Over Ethernet is presented. All ports on an ATA server are assigned a same Media Access Control (MAC) address. When the first switch receives a packet destined to the second switch the first switch performs a route lookup on a destination address of the packet and forwards the packet to the target over one of the second plurality of links, and when the second switch receives a packet destined to the first switch the second switch performs a route lookup on a destination address of the packet and forwards the packet to the target over one of the second plurality of links.

Abstract: A bitmask array is implemented as a two dimensional bit array where each bit represents an allocated/free cell of the heap. Groups of bits of the bitmask array are assigned to implement commonly sized memory cell allocation requests. The heap manager keeps track of allocations by keeping separate lists of which groups are being used to implement commonly sized memory cell allocations requests by maintaining linked lists according to the number of cells allocated per request. Each list contains a list of the bit groups that have been used to provide allocations for particularly sized requests. By maintaining lists based on allocation size, the heap manager is able to cause new allocation requests to be matched up with previously retired allocations of the same size. Memory may be dynamically allocated between lists of differently sized memory requests.

Abstract: Packet processing is broken into two or more stages. In particular, the network processing unit 26 performs a first stage of packet processing related to packet forwarding and packet modification, and then performs a second stage of packet processing unrelated to packet forwarding and packet modification. Example processes unrelated to packet forwarding and packet modification may include state updates on the network element, such as statistics counter updates, stateful flow tracking, IPFix processing, MAC learning, and other processes important to operation of the network element, but which do not affect the appearance of the packet (e.g. packet format) and which do not affect the forwarding decision of the packet. Once the first stage of packet processing related to packet forwarding and packet modification has been completed, the flag associated with the packet is cleared in the scoreboard, to allow the packet to be transmitted from the reorder queue.

Abstract: A method for specifying packet address range cacheability is provided. The method includes passing a memory allocation request from an application running on a network element configured to implement packet forwarding operations to an operating system of a network element, the memory allocation request including a table ID associated with an application table to be stored using the memory allocation. The method also includes allocating a memory address range by the operating system to the application in response to the memory allocation request, and inserting an entry in a cacheability register, the entry including the table ID included in the memory allocation request and the memory address range allocated in response to the memory allocation request.

Abstract: A method, apparatus and computer program product for Media Access Control (MAC) address learning and learning rate suppression are presented. A Forwarding Data Unit (FDU) maintains two cache tables, each of the cache tables used for harvesting MAC addresses. The FDU uses the cache tables in an alternating manner, wherein when one of the cache tables is used for harvesting MAC addresses the other one of the cache tables has its contents bundled into a packet for forwarding to a control plane of the FDU.

Abstract: A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a configuration bit vector wherein each bit in the configuration bit vector corresponds to a respective feature. When said branch flag returns a first result processing is continues at an instruction located at a first location relative to a Program Counter (PC) and when the branch flag returns a second result processing is continued at a second location relative to said PC.

Abstract: Packets are colored and stored in a shared packet buffer without assigning fixed page allocations per port. The packet buffer is divided into three areas—an unrestricted area, an enforced area, and a headroom area. Regardless of the fullness level, when a packet is received it will be stored in the packet buffer. If the fullness level is in the unrestricted area, no flow control messages are generated. If the fullness level is in the enforced region, a probabilistic flow control generation process is used determine if a flow control messages will be generated. If the fullness level is in the headroom area, flow control is automatically generated. Quanta timers are used to control regeneration of flow control messages.

Abstract: A method, apparatus and computer readable medium for maintaining two variables per port member of a network device which is part of a Split Multi Link Trunk/Link Aggregation Group (SMLT/LAG) is presented. A first variable comprising a link status variable reflecting a link status, and a second variable comprising a forwarding status variable reflecting a forwarding status of a forwarding plane with respect to the port are provided, the link status variable and the forwarding status variable in a first state when the port is operating properly. A failure related to the port is detected. The link status variable is set to a second state, and the forwarding status variable is set to a second state.

Abstract: A method, apparatus and computer program product for performing TCAM lookups in multi-threaded packet processors is presented. A Ternary Content Addressable Memory (TCAM) key is constructed for a packet and a Packet Reference Number (PRN) is generated. The TCAM key and the packet are tagged with the PRN. The TCAM key and the PRN are sent to a TCAM and in parallel the packet and the PRN are sent to a packet processing thread. The PRN is used to read the TCAM result when it is ready.

Abstract: Prefix length memory tables are used to enable fast IPv4 LPM lookups using a single memory access for a first range of IP prefixes, and using two memory accesses for larger IP prefixes. Each of the prefix length memory tables is used to hold a set of forwarding rules associated with a different prefix length range. IP LPM operations are then performed in parallel in each of the prefix length memory tables of the set, and the forwarding rule matching the longest prefix is returned from each of the memory tables. A priority encoder is used to select between positive results from the multiple prefix length memory tables to enable the forwarding rule with the largest matching prefix to be used to key into the next hop forwarding table. The method utilizes low cost DDR SDRAM rather than TCAM, and also exhibits low overhead.

Abstract: A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality of memory First In First Out (FIFO) buffers, each of the memory FIFO buffers in communication with a memory controller. The memory access requests are distributed evenly across said memory banks by way of the memory controller. This reduces and/or eliminates memory latency which can occur when sequential memory operations are performed on the same memory bank.