Patents by Inventor Hamid Ghezel

Hamid Ghezel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9819478
    Abstract: In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: November 14, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Vinh Ho, Qin Wei, Magathi Jayaram, Hamid Ghezel
  • Patent number: 9490778
    Abstract: In one embodiment, a voltage-controlled oscillator has a ring of delay stages and power-regulating circuitry regulating power to each delay stage. Each delay stage has at least one inverter having a leg having a current regulator that controls current flowing through the leg and thereby controlling gain of the delay stage. The VCO receives three control signals that affect the amount of delay applied by each delay stage and therefore the VCO output frequency: a first applied to control the power-regulating circuitry, a second applied to at least one transistor gate in the current regulator, and a third applied to at least one transistor body in the current regulator. The power-regulating circuitry has a parallel configuration of a power-regulating transistor, a first capacitor, and a switched-capacitor leg having a second capacitor and a switch for controlling settling time. The capacitors regulate the power supply without a dedicated, opamp-based voltage regulator.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 8, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Vinh Ho, Magathi Jayaram, Hamid Ghezel, David Li
  • Publication number: 20160134264
    Abstract: In an integrated circuit, meta-stability prevention circuitry prevents an oscillator, such as a current-controlled oscillator having a ring of differential inverters, from being turned on, for example, during power up, until after the power-supply voltage is sufficiently high for the oscillator ring to achieve oscillation without going into a meta-stable state. In one implementation, a level detector monitors the power-supply voltage level and generates a logic signal indicating whether or not the power-supply voltage level is sufficiently high. That logic signal and a conventional chip-level power-down control signal are applied to logic circuitry that generates control signals for one or more switch transistors that selectively turn on and off the oscillator ring.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Inventors: Maryam Shahbazi, Hamid Ghezel, Ban Pak Wong, Magathi Jayaram
  • Patent number: 9197237
    Abstract: In one embodiment, a loss-of-signal detector is provided that is immune to variations in common mode voltage for a received differential input signal. The loss-of-signal detector is configured is to use a reference voltage that depends upon the common mode voltage.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: November 24, 2015
    Assignee: Lattice Semiconductor Corporation
    Inventors: Vinh Ho, Hamid Ghezel
  • Publication number: 20140105265
    Abstract: In one embodiment, a loss-of-signal detector is provided that is immune to variations in common mode voltage for a received differential input signal. The loss-of-signal detector is configured is to use a reference voltage that depends upon the common mode voltage.
    Type: Application
    Filed: April 23, 2013
    Publication date: April 17, 2014
    Applicant: Lattice Semiconductor Corporation
    Inventors: Vinh Ho, Hamid Ghezel