Abstract: A method for monitoring and/or controlling a biopharmaceutical process includes querying, based on a first spectral scan vector of the biopharmaceutical process, an observation database comprising observation data sets associated with past scans. Each of the observation data sets includes spectral data and a corresponding actual analytical measurement. Querying the observation database includes determining first parameters defining a set of distributions for the first spectral scan vector, and selecting as training data, from among the observation data sets, particular observation data sets based on (i) the first parameters and (ii) other parameters defining respective sets of distributions for the observation data sets. The method also includes calibrating, using the selected training data, a local model specific to the biopharmaceutical process.

Abstract: A method of controlling a cell culture process uses hybrid predictive modeling in a model predictive controller. The method includes, for multiple time intervals, obtaining current values of cell culture attributes associated, and generating a control value for a physical input to the cell culture process. Generating the control value includes predicting future values of the cell culture attributes based on the current values, by using one or more data-driven models to predict future values of a first one or more attributes of the cell culture attributes, and using one or more first principle models to predict future values of a second one or more attributes of the cell culture attributes. Generating the control value also includes determining the control value by optimizing an objective function subject to the predicted future values. The method also includes using the control value to control the physical input to the cell culture process.

Abstract: A method of controlling a cell culture process includes, for each time interval of one or more time intervals during the cell culture process, obtaining current values of one or more cell culture attributes associated with a cell culture, predicting one or more future values of a particular cell culture attribute associated with the cell culture, and controlling one or more physical inputs to the cell culture process. Predicting the future value(s) includes applying the current values of the cell culture attribute(s), and an earlier value of at least one of the cell culture attributes, as inputs to a data-driven predictive model using historical data. Controlling the physical input(s) includes applying the future value(s) as inputs to a model predictive controller.

Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element; power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.

Abstract: Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.

Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.

Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.

Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.

Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Abstract: Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.

Abstract: A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.

Abstract: A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Abstract: A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Abstract: An embodiment of the present invention is directed to a system including a memory interface logic unit for receiving memory access requests and corresponding information, a processor coupled to the memory interface logic, a plurality of pre-fetch buffers for handling memory accesses coupled to the memory interface logic unit, an arbiter logic unit for pre-fetching data into the plurality of pre-fetch buffers, a memory device for storing data coupled to the arbiter logic unit and the plurality of pre-fetch buffers, and busy detection logic for informing the arbiter logic unit of the current operation of the processor. The arbiter logic unit facilitates memory access via pre-fetch buffers of the processor and the memory in different or independent clock domains. The arbiter logic further allows random access without introducing additional latency.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.

Abstract: A controller circuit provides communication paths between multiple host devices and a target device. The controller circuit includes a first host idle detection circuit that determines when a first host interface (I/F) is in an idle state, an idle state being when the first host I/F is not communicating with the controller circuit. A switch circuit can selectively enables a controllable communication path between a second host I/F and a target device I/F. A first response circuit can be coupled to the first host I/F and output predetermined responses from the first host I/F in response to communications received on the first host I/F. The first response circuit outputting a predetermined response when at least the controller circuit has enabled the controllable communication path between a second host I/F and the target device I/F and disabled the controllable communication path between the first host I/F and the target device I/F.