Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract: Systems and methods provide multi-use input/output (I/O) pads for an integrated circuit. For example in accordance with an embodiment, the multi-use pads may be shared to support different integrated circuit functions via the pads, such as selectively for high-speed signaling or general I/O.

Abstract: A method and apparatus for power amplifier gain control is provided, such as may be embodied as an integrated circuit is disclosed. Embodiments provide for a continuously variable gain control at low cost as contrasted two-state or multi-state capabilities of previously developed solutions. Improved consistency and control over gain may be provided using features disclosed.

Abstract: A method and apparatus for an amplifier, such as a radio frequency amplifier embodiment as an integrated circuit is disclosed. Embodiments provide for operating with good energy efficiency at multiple power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. A compensating impedance is switched into or out of circuit in high power mode to improve the match that would pertain without the compensation. Improved compensation and linearity may be provided using features disclosed. The invention may operate in the microwave region or at other RFs.

Abstract: A method and apparatus for a temperature compensated bias network, such as may be embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of desired temperature characteristics with good stability. Current mirror components with active leakage circuits may act to provide consistent operating parameters over a wide range of temperatures. Improved compensation and linearity may be provided using features disclosed.

Abstract: A method and apparatus for an amplifier, such as a radio frequency amplifier embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of operating powers with good energy efficiency at many power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. The invention may operate in the microwave region or at other RFs.

Abstract: A semiconductor device includes a semiconductor substrate, an electrode disposed on an upper surface of the substrate, and a set of one or more transistor element(s) disposed on the upper surface of the substrate. The set of transistor element(s) compactly surrounds the electrode with a threshold distance. In one embodiment, the set also compactly surrounds a via hole. In another, the element(s) comprises a bipolar junction transistor that has an aggregate emitter length of not less than 10 microns. In still another embodiment, the device is coupled to a RF circuit for power amplification.

Abstract: A method and apparatus for a variable gain cascode amplifier (or attenuator) is disclosed. Embodiments provide for a compensated input impedance. A gain/impedance controller compensates input impedance corresponding to gain adjustments.

Abstract: A method for designing at least one mask for manufacturing an integrated circuit is disclosed. The method may include generating a schematic; entering data representing transistors of the set into a computer-aided design system; identifying transistors expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail; designating robust geometries such transistors and operating the computer-aided design system to generate mask or masks. Integrated circuits of scalable design are also disclosed.

Abstract: The invention relates to inductors in integrated circuits. Methods and apparatuses for semiconductor circuits and microcircuits that include on-chip inductive elements which may form general impedance blocks are disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, an electrode disposed on an upper surface of the substrate, and a set of one or more transistor element(s) disposed on the upper surface of the substrate. The set of transistor element(s) compactly surrounds the electrode with a threshold distance. In one embodiment, the set also compactly surrounds a via hole. In another, the element(s) comprises a bipolar junction transistor that has an aggregate emitter length of not less than 10 microns. In still another embodiment, the device is coupled to a RF circuit for power amplification.

Abstract: There is provided an antibody granule, consisting essentially of one or more antibodies, or fragments derived thereof, granulated with an alkali metal salt. Also provided is a process for preparing said antibody granules. The granules can be used in an enzymatic stain bleaching or anti dye-transfer composition.

Abstract: A method and apparatus for a variable gain cascode amplifier (or attenuator) is disclosed. Embodiments provide for a compensated input impedance. A gain/impedance controller compensates input impedance corresponding to gain adjustments.

Abstract: A method for designing at least one mask for manufacturing an integrated circuit disclosed. The method may include generating a schematic; entering data representing transistors of the set into a computer-aided design system; identifying transistors expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail; designating robust geometries such transistors and operating the computer-aided design system to generate mask or masks. Integrated circuits of scalable design are also disclosed.