Abstract: In one embodiment, a circuit for communicating with a memory is provided. The circuit includes a sorting circuit configured to receive a plurality of read and write transactions. The sorting circuit sorts the write transactions according to respective sizes of data to be written to the memory, and sorts the read transactions according to respective sizes of data to be read from the memory. A selection circuit is configured to select transactions for transmission to the memory, from the sorted read and write transactions, in an order that balances a quantity of data to be written to the memory over a first serial data link with a quantity of data to be read from the memory over a second serial data link. A transmitter is coupled to the selection circuit and is configured to transmit the selected transactions to the memory device on a serial data link.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath is configured to operate at two frequencies to accommodate the programmable circuitry in the integrated circuit.

Abstract: A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.

Abstract: A media access controller system embedded in an integrated circuit is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in an integrated circuit. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Abstract: A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory. These mechanisms enable a range of very cost effective small memory subsystems that support ECC operation in a minimum of standard commodity memory devices. ECC encoding is provided to support efficient byte write operations.

Abstract: A transmit-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a transmit engine. A transmit-side datapath is coupled to the media access controller core. The transmit-side datapath is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.

Abstract: A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.

Abstract: An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

Abstract: Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block) located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

Abstract: A method for implementing wide gates and tristate buses using FPGA carry logic. Wide gate logic functions and tristate buses are detected and implemented with a plurality of LUTs and carry multiplexers. The wide gate functions are of the form: Ff=((( . . . (f0 $ f1) $ f2) $ f3) . . . ) $ fm, where $ represents a logic operator such as AND, OR or XOR. Thus the method includes the commonly used functions FAND=i1 AND i2 AND i3 AND . . . in; and FOR=i1 OR i2 OR i3 . . . in.as well as many mixed functions. The LUTs implement the respective portions of functions f0 through fm and the carry multiplexers implement the logic operators that connect the functions in a cascaded manner. A tristate bus definition includes a plurality of bus input signals and a plurality of bus select signals, each of the bus input signals associated with one or more of the bus select signals.

Abstract: An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. The configuration control circuit includes a controlling circuit (e.g., a PLD) and a memory circuit (e.g., a PROM). The PROM is configured with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the RAM. The control function also generates a reconfiguration signal responsive to a first predetermined condition.