Abstract: A processing device including a primary processing unit and at least one secondary processing unit, the primary processing unit being designed to subject primary digital input data to a predefinable first data processing, the secondary processing unit being designed to subject secondary digital input data to a predefinable second data processing, the processing device being designed to delay the second data processing by the at least one secondary processing unit at least intermittently in relation to the first data processing by the primary processing unit.

Abstract: A method for generating a challenge-response pair in an electric machine as a basis for an identification or authentication is described, the electric machine having a stator and a rotor, a first alternating voltage between two points of a first defined point pair of the electric machine being applied as a challenge, which causes an induction in the electric machine, a variable dependent on the caused induction being determined as a response. The first alternating voltage has a frequency which is higher than the working frequency of the electric machine.

Abstract: A processing device including a primary processing unit and at least one secondary processing unit, the primary processing unit being designed to subject primary digital input data to a predefinable first data processing, the secondary processing unit being designed to subject secondary digital input data to a predefinable second data processing, the processing device being designed to delay the second data processing by the at least one secondary processing unit at least intermittently in relation to the first data processing by the primary processing unit.

Abstract: A processing device including a primary processing unit and at least one secondary processing unit, the primary processing unit being designed to subject primary digital input data to a predefinable first data processing, whereby primary digital output data are obtained, the secondary processing unit being designed to subject secondary digital input data to a predefinable second data processing, whereby secondary digital output data are obtained, and the processing device being designed to at least intermittently invert the primary digital input data to obtain the secondary digital input data.

Abstract: A method for operating a control device having a system-on-a-chip having a processor unit and a security processor unit, the processor unit and the security processor unit each having at least one processor core, the processor unit instructing the security processor unit to execute security-critical processes, a priority being assigned, by the processor unit or by the security processor unit, to each of the security-critical processes that are to be executed in the security processor unit, and the security-critical processes being executed in the security processor unit as a function of the respective priority.

Abstract: In a counter mode encryption scheme, a sending device sends a first message including first cipher text and a first counter used to generate the first cipher text to a receiving device for decryption. The sending device subsequently generates a second counter for generating second cipher text. The sending device sends a second message including the second cipher text and intermediate state data corresponding to a change between the first counter second counter to the receiving device for decryption. The intermediate state data are represented by a smaller number of bits than the first counter. The method enables improved counter mode encrypted communication in networks that lose one or more intermediate messages between the first message and the second message.

Abstract: In a counter mode encryption scheme, a sending device sends a first message including first cipher text and a first counter used to generate the first cipher text to a receiving device for decryption. The sending device subsequently generates a second counter for generating second cipher text. The sending device sends a second message including the second cipher text and intermediate state data corresponding to a change between the first counter second counter to the receiving device for decryption. The intermediate state data are represented by a smaller number of bits than the first counter. The method enables improved counter mode encrypted communication in networks that lose one or more intermediate messages between the first message and the second message.

Abstract: A method for generating a challenge-response pair in an electric machine as a basis for an identification or authentication is described, the electric machine having a stator and a rotor, a first alternating voltage between two points of a first defined point pair of the electric machine being applied as a challenge, which causes an induction in the electric machine, a variable dependent on the caused induction being determined as a response. The first alternating voltage has a frequency which is higher than the working frequency of the electric machine.

Abstract: Administration module, producer and consumer processor, arrangement thereof and method for inter-processor communication via a shared memory, wherein the module includes: a device for storing and administering the states of triple-buffers, each buffer having a read-, a write- and an idle-sub-buffer; a device for communicating with at least one producer and at least one consumer processor, and wherein the administration device is formed to determine a targeted read- or write-sub-buffer from the triple-buffers in response to a producer or consumer processor access.