Abstract: A spatially unrolled time domain (TD) architecture that includes an input and weight register having i inputs and j weights, where i corresponds with a number of delay lines for i neurons, and j corresponds with a number of processing elements (PEs) for each delay line of the i delay lines. An enable control register sends a global input pulse to i neurons, and each delay line of the i delay lines includes the corresponding j PEs for that delay line. Each PE includes a digital-to-time converter (DTC) that accepts a digital input and weight and generates a relative delay, each time delay within a given delay line contributing to an overall delay for the given delay line. i time-to-digital converters (TDCs). A readout register receives digital outputs from each of the i TDCs, and serially outputs a signal from each of the i delay lines based on the overall time delay for each of the i delay lines.