Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.

Abstract: A wall-mountable aquarium has a slim tank for containing water to keep living aquatic animals or plants. The tank includes a transparent front wall, a rear wall, opposite left and right side walls and a bottom wall, with the side and bottom walls being considerably narrower than the front and rear walls. A fixed enclosure is provided externally on at least one of the left and right side walls and bottom wall for containing part of accessory for the aquarium. A frame is attached on the front wall, which conceals the enclosure from direct sight from the front and includes a see-through portion therein to reveal only the living habitat inside the tank through the front wall.

Abstract: A background setting for an aquarium having front and rear walls and opposite left and right side walls. The setting comprises a water-resistant background sheet bearing a background scenery for direct submersion in the water of the aquarium to cover the rear wall, and a fixture for fixing the background sheet inside the aquarium.

Abstract: A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.

Abstract: A method is adapted to form wire interconnect pads on integrated circuit devices and includes the steps of providing a semiconductor substrate having an aluminum-copper top metal layer, and a titanium nitride layer covering the aluminum-copper top metal layer, and a photoresist coating applied to the titanium nitride layer. The photoresist coating is partially exposed and partially developed to form openings for etching an array of submicron size holes. Etching through the titanium nitride layer to the aluminum-copper layer, by way of the partially developed photoresist, forms a rough textured surface profile in the array of cavities, with diameters of less than 0.3 um, etched in the aluminum copper layer. After stripping of the photoresist and depositing a passivation film, windows are formed delineating improved bond pads for wire bonding. The textured cavities increase the surface area of the bond pads and provide improved bondability for the 0.35 and 0.3 um IC devices.