Patents by Inventor Han-Chin Chiu

Han-Chin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11784237
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 10, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Kingyuen Wong, Han-Chin Chiu, Ming-Hong Chang, Chunhua Zhou, Jinhan Zhang
  • Patent number: 11776934
    Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: October 3, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: Han-Chin Chiu
  • Patent number: 11757005
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Ming-Wei Tsai, Han-Chin Chiu
  • Publication number: 20230072850
    Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.
    Type: Application
    Filed: April 12, 2021
    Publication date: March 9, 2023
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Patent number: 11594606
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Patent number: 11575021
    Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
  • Patent number: 11563097
    Abstract: The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 24, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Ming-Hong Chang, Kingyuen Wong, Han-Chin Chiu, Hang Liao
  • Publication number: 20220399443
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.
    Type: Application
    Filed: July 16, 2020
    Publication date: December 15, 2022
    Inventor: Han-Chin CHIU
  • Patent number: 11522066
    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Publication number: 20220375876
    Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.
    Type: Application
    Filed: April 12, 2021
    Publication date: November 24, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220376050
    Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a first area and a second area, and the second nitride semiconductor layer has single crystals. The semiconductor device includes an electrode in contact with the first area. A first concentration of Aluminum (Al) of the first area is less than a second concentration of Al of the second area, and the single crystals in the first area take over a crystal structure of the first nitride semiconductor layer.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 24, 2022
    Inventor: Han-Chin CHIU
  • Publication number: 20220328424
    Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first group III element and is devoid of a second group III element. The buffer layer includes a III-V compound which includes the first and second group III elements. The buffer layer has an element ratio of the first group III element to the second group III element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328678
    Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328672
    Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from narrow to wide with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.
    Type: Application
    Filed: July 20, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328677
    Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. An oscillation rate in the concentration of the first element per unit thickness of the buffer layer varies with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.
    Type: Application
    Filed: July 20, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328425
    Abstract: A semiconductor device includes a nucleation layer, a first buffer layer, a first nitride-based semiconductor layer, and a second buffer layer. The nucleation layer includes a compound which includes a first element. The first buffer layer includes a III-V compound which includes the first element. A concentration of the first element varies with respect to a first reference point within the first buffer layer. The first nitride-based semiconductor layer is disposed on the first buffer layer. The second buffer layer includes a III-V compound which includes a second element different than the first element. The second buffer layer is disposed on and forms an interface with the first nitride-based semiconductor layer. A concentration of the second element varies to cyclically oscillate as a function of a distance within a thickness of the second buffer layer, which occurs with respect to a second reference point within the second buffer layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328680
    Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element cyclically oscillating with respect to first and second reference points within a buffer layer. The first and second reference points are respectively positioned at first and second distances from a top surface of the nucleation layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328675
    Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is greater than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.
    Type: Application
    Filed: July 20, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328676
    Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is less than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.
    Type: Application
    Filed: July 20, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
  • Publication number: 20220328679
    Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN