Patents by Inventor Han-Chin Chiu
Han-Chin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12148713Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.Type: GrantFiled: April 12, 2021Date of Patent: November 19, 2024Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Yi-Lun Chou, Kye Jin Lee, Han-Chin Chiu, Xiuhua Pan
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Patent number: 12125902Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first group III element and is devoid of a second group III element. The buffer layer includes a III-V compound which includes the first and second group III elements. The buffer layer has an element ratio of the first group III element to the second group III element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.Type: GrantFiled: July 26, 2021Date of Patent: October 22, 2024Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Yi-Lun Chou, Kye Jin Lee, Han-Chin Chiu, Xiuhua Pan
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Patent number: 12125801Abstract: A semiconductor device includes a nucleation layer, a first buffer layer, a first nitride-based semiconductor layer, and a second buffer layer. The nucleation layer includes a compound which includes a first element. The first buffer layer includes a III-V compound which includes the first element. A concentration of the first element varies with respect to a first reference point within the first buffer layer. The first nitride-based semiconductor layer is disposed on the first buffer layer. The second buffer layer includes a III-V compound which includes a second element different than the first element. The second buffer layer is disposed on and forms an interface with the first nitride-based semiconductor layer. A concentration of the second element varies to cyclically oscillate as a function of a distance within a thickness of the second buffer layer, which occurs with respect to a second reference point within the second buffer layer.Type: GrantFiled: July 26, 2021Date of Patent: October 22, 2024Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Yi-Lun Chou, Kye Jin Lee, Han-Chin Chiu, Xiuhua Pan
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Publication number: 20240297227Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Applicant: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventor: Han-Chin CHIU
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Patent number: 12068373Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a first area and a second area, and the second nitride semiconductor layer has single crystals. The semiconductor device includes an electrode in contact with the first area. A first concentration of Aluminum (Al) of the first area is less than a second concentration of Al of the second area, and the single crystals in the first area take over a crystal structure of the first nitride semiconductor layer.Type: GrantFiled: August 7, 2020Date of Patent: August 20, 2024Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventor: Han-Chin Chiu
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Patent number: 12021121Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.Type: GrantFiled: July 16, 2020Date of Patent: June 25, 2024Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventor: Han-Chin Chiu
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Patent number: 11984486Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.Type: GrantFiled: January 23, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
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Patent number: 11784237Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.Type: GrantFiled: December 20, 2019Date of Patent: October 10, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Kingyuen Wong, Han-Chin Chiu, Ming-Hong Chang, Chunhua Zhou, Jinhan Zhang
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Patent number: 11776934Abstract: A semiconductor apparatus includes a channel layer, a barrier layer, a source contact and a drain contact, a first doped group III-V semiconductor, a group III-V semiconductor, and a second doped group III-V semiconductor. The barrier layer is disposed on the channel layer. The source contact and the drain contact are disposed on the channel layer. The first doped group III-V semiconductor is disposed on the barrier layer. The group III-V semiconductor is disposed on the first doped group III-V semiconductor and between the source contact and the drain contact. The second doped group III-V semiconductor is disposed on the group III-V semiconductor and between the source contact and the drain contact. The group III-V semiconductor has a central region covered by the second doped group III-V semiconductor and a peripheral region free from coverage by the second doped group III-V semiconductor.Type: GrantFiled: May 23, 2022Date of Patent: October 3, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventor: Han-Chin Chiu
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Patent number: 11757005Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.Type: GrantFiled: May 19, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Ming-Wei Tsai, Han-Chin Chiu
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Publication number: 20230072850Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.Type: ApplicationFiled: April 12, 2021Publication date: March 9, 2023Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
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Patent number: 11594606Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.Type: GrantFiled: February 3, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
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Patent number: 11575021Abstract: A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.Type: GrantFiled: May 10, 2021Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
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Patent number: 11563097Abstract: The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.Type: GrantFiled: December 27, 2019Date of Patent: January 24, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Ming-Hong Chang, Kingyuen Wong, Han-Chin Chiu, Hang Liao
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Publication number: 20220399443Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure and a conductive layer. The substrate has a first surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The conductive layer is disposed on the second nitride semiconductor layer. The conductive layer has a first length extending in a first direction substantially parallel to the first surface of the substrate, a second length extending in a second direction substantially perpendicular to the first direction—from a cross section view perspective—wherein the second length is greater than the first length.Type: ApplicationFiled: July 16, 2020Publication date: December 15, 2022Inventor: Han-Chin CHIU
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Patent number: 11522066Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.Type: GrantFiled: December 8, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Publication number: 20220375876Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.Type: ApplicationFiled: April 12, 2021Publication date: November 24, 2022Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
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Publication number: 20220376050Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer on the substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a first area and a second area, and the second nitride semiconductor layer has single crystals. The semiconductor device includes an electrode in contact with the first area. A first concentration of Aluminum (Al) of the first area is less than a second concentration of Al of the second area, and the single crystals in the first area take over a crystal structure of the first nitride semiconductor layer.Type: ApplicationFiled: August 7, 2020Publication date: November 24, 2022Inventor: Han-Chin CHIU
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Publication number: 20220328424Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer includes a compound which includes a first group III element and is devoid of a second group III element. The buffer layer includes a III-V compound which includes the first and second group III elements. The buffer layer has an element ratio of the first group III element to the second group III element that incrementally increases and then decrementally decreases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.Type: ApplicationFiled: July 26, 2021Publication date: October 13, 2022Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN
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Publication number: 20220328679Abstract: A semiconductor device includes a substrate, a nucleation layer, a buffer layer, first and second nitride-based semiconductor layers, a pair of S/D electrodes, and a gate electrode. The nucleation layer is disposed on the substrate. The buffer layer includes a III-V compound which includes a first element. The buffer layer is disposed on the nucleation layer. The buffer layer has a variable concentration of the first element that decrementally decreases and then incrementally increases as a function of a distance within a thickness of the buffer layer. The first nitride-based semiconductor layer is disposed on the buffer layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.Type: ApplicationFiled: July 26, 2021Publication date: October 13, 2022Inventors: Yi-Lun CHOU, Kye Jin LEE, Han-Chin CHIU, Xiuhua PAN