Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Abstract: A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.

Abstract: A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.

Abstract: The present invention provides a method for fabricating a CMOS image sensor including a plurality of steps. Firstly, a substrate is provided. Then, a pixel region covering most of the substrate and a logic circuit region on a periphery of the substrate are formed. After that, at least one trench is formed in the pixel region. Next, a deposition process is performed to fill the at least one trench and cover the pixel region. Then, a planarization process is performed to expose a surface of the pixel region. A first treatment on the exposed surface of the pixel region is next performed by applying a first cleaning solution including hydrogen fluoride (HF) and ethylene glycol (EG). Besides, an amount of HF is lesser than that of EG.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a memory region and a periphery region; forming a memory cell on the memory region; forming a first polysilicon layer on the periphery region and the memory cell; forming a patterned cap layer on the periphery region; forming a second polysilicon layer on the first polysilicon layer and the patterned cap layer; and performing a chemical mechanical polishing (CMP) process to remove the second polysilicon layer, wherein the chemical mechanical polishing process comprises an abrasive of greater than 13% and a remove rate of less than 30 Angstroms/second.

Abstract: A polishing method of a semiconductor device is disclosed. A substrate having a first side and a second side opposite to the first side is provided. The substrate has a device layer formed on the first side and a plurality of trench isolation structures therein extending from the first side to the second side. A main polishing step is performed to the second side of the substrate until a surface of at least one of the trench isolation structures is exposed. An auxiliary polishing step is then performed to the second side of the substrate. Besides, a silicon-to-oxide selectivity of the main polishing step is different from a silicon-to-oxide selectivity of the auxiliary step.

Abstract: A method of fabricating an isolation structure of a semiconductor device includes the following steps. Firstly, a substrate including a first surface and a second surface is provided. At least one trench is formed in the first surface of the substrate. The trench has a sidewall and a bottom surface. Then, a first chemical vapor deposition process is performed to form a first isolation layer on the first surface of the substrate and the sidewall and the bottom surface of the trench. Then, an anisotropic surface treatment process is performed, so that a surface of the first isolation layer has differential surface chemical properties. Afterwards, a second chemical vapor deposition process is performed to form a second isolation layer on the first isolation layer with a surface having differential surface chemical properties.

Abstract: A method for forming a semiconductor structure and a method for patterning a dielectric layer are provided. The method comprises following steps. An upper cap layer is formed on and physically contacted with a dielectric layer. The dielectric layer has a dielectric thickness having a range of 1000 ?˜5000 ?. A patterned mask layer is formed on and physically contacted with the upper cap layer. A part of the upper cap layer is removed to form a patterned upper cap layer by using the patterned mask layer as an etching mask. A part of the dielectric layer is removed to form a dielectric opening in the dielectric layer by using the patterned upper cap layer as an etching mask.

Abstract: A method of forming interlayer dielectric comprising the steps of forming a first undoped layer, forming in-situ and sequentially a doped layer and a second undoped layer on the first undoped layer, and planarizing the second undoped layer.

Abstract: A method for cleaning a reaction chamber having a pedestal and a carrier ring is provided. First, the pedestal and the carrier ring are cleaned with a high pressure gas. Next, the carrier ring is moved to leave the pedestal, and a low pressure gas is provided to clean the pedestal, the carrier ring, and an area lay between the pedestal and the carrier ring. Thereafter, a full flush is performed to clean the pedestal and the carrier ring.