Patents by Inventor Han Chuang
Han Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250254921Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes channel structures vertically separated from each other and a gate structure wrapping around the channel structures. The semiconductor structure further includes a first porous layer formed over a first sidewall of the gate structure under the channel structures and a source/drain structure attached to the channel structures. In addition, the source/drain structure is laterally separated from the first porous layer by a first air gap.Type: ApplicationFiled: June 4, 2024Publication date: August 7, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Han CHUANG, Jung-Hung CHANG, Shih-Cheng CHEN, Chien-Ning YAO, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250254912Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A source/drain recess is formed in the semiconductor fin. A first isolation sidewall dielectric and a second isolation sidewall dielectric are formed lining opposite sidewalls of the source/drain recess. An epitaxial layer is formed in the source/drain recess. The epitaxial layer is recessed such that a top surface of the epitaxial layer is lower than top surfaces of the first and second isolation sidewall dielectrics. An epitaxial source/drain region is formed on the recessed epitaxial layer. A gate structure is formed adjacent the epitaxial source/drain region.Type: ApplicationFiled: February 7, 2024Publication date: August 7, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng CHEN, Wen-Ting LAN, Jung-Hung CHANG, Tsung-Han CHUANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG
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Patent number: 12374639Abstract: A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.Type: GrantFiled: May 27, 2022Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Yang Lin, Chen-Yu Liu, Yung-Han Chuang, Ming-Da Cheng, Ching-Yu Chang
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Patent number: 12370117Abstract: An exoskeleton robotic equipment for tenodesis grasp and release training includes an exoskeleton mechanism and a control device. The exoskeleton mechanism includes a fixing seat worn on a forearm, an actuator device mounted to the fixing seat, and a transmission module connected to the fixing seat and pivotally connected to the actuator device and cooperating with the fixing seat and the actuator device to form a four-bar linkage mechanism. The actuator device is controlled by the control device to drive the transmission module to move relative to the fixing seat to change the transmission module into a release state and into a grasp state so as to move the index finger and the middle finger away from and toward the thumb.Type: GrantFiled: June 4, 2021Date of Patent: July 29, 2025Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Hsiu-Yun Hsu, Chien-Hsien Yeh, Kang-Chin Yang, Ping-Han Chuang, Fong-Chin Su, Li-Chieh Kuo
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Publication number: 20250234603Abstract: A semiconductor structure includes a plurality of nanosheets, a gate structure, an S/D structure, a stepped structure, and a sidewall spacer. The plurality of nanosheets is disposed over a substrate, wherein the substrate extends along a first direction, and the nanosheets are arranged along a second direction substantially perpendicular to the first direction. The gate structure is disposed over the substrate, wherein the gate structure is disposed between and surrounding the nanosheets. The S/D structure is disposed adjacent to the gate structure and the plurality of nanosheets. The stepped structure is disposed below the S/D structure, wherein the stepped structure overlaps at least one of the nanosheets along the first direction. The sidewall spacer is disposed between the stepped structure and the at least one of the nanosheets. A method of manufacturing the semiconductor structure is also provided.Type: ApplicationFiled: January 11, 2024Publication date: July 17, 2025Inventors: TSUNG-HAN CHUANG, JUNG-HUNG CHANG, CHIA-CHENG TSAI, SHIH-CHENG CHEN, KUO-CHENG CHIANG, CHIH-HAO WANG
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Patent number: 12357226Abstract: Described herein are systems and methods for determining medical staffing requirements for administering OIT to patients. Specifically, the methods and systems disclosed herein can determine the time required by a medical staff at a given treatment location to devote to administering OIT to patients as well as the number of patients undergoing OIT over a selected time period. The methods and systems disclosed herein can further provide the time required by providers and clinical staff at a given treatment location to devote to administering OIT to patients.Type: GrantFiled: June 30, 2021Date of Patent: July 15, 2025Assignee: Société des Produits Nestlé S.A.Inventors: Hans Chuang, Brian Greenblatt, Richard Smith, Marisa Crowell, Varsha Damle, Chantale Bielak, Robert Grossi, Joy Mabon
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Publication number: 20250212479Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures formed over a substrate along a first direction, and a gate structure formed over the nanostructures along a second direction. The semiconductor structure includes an S/D structure formed adjacent to the gate structure, and a plurality of inner spacer layers between the gate structure and the S/D structure. The semiconductor structure includes a hard mask layer formed on the inner spacer layers, and a top surface of the hard mask layer is higher than a top surface of the S/D structure.Type: ApplicationFiled: December 26, 2023Publication date: June 26, 2025Inventors: Shih-Cheng CHEN, Wen-Ting LAN, Jung-Hung CHANG, Tsung-Han CHUANG, Chia-Cheng TSAI, Kuo-Cheng CHIANG
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Patent number: 12342587Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.Type: GrantFiled: March 11, 2022Date of Patent: June 24, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Zhi-Chang Lin, Chien Ning Yao, Shih-Cheng Chen, Jung-Hung Chang, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12334425Abstract: An electronic package is provided, in which a mesh structure is disposed between a circuit structure and an electronic element to increase the shunt path of current. Therefore, when the electronic element is used as an electrode pad of a power contact, the current can be passed through a conductive sheet of the circuit structure via the mesh structure, such that the power loss can be reduced and the IR drop of the electronic element can meet the requirements.Type: GrantFiled: November 16, 2022Date of Patent: June 17, 2025Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang
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Patent number: 12336226Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.Type: GrantFiled: March 3, 2022Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Tsung-Han Chuang, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20250183204Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.Type: ApplicationFiled: January 30, 2025Publication date: June 5, 2025Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
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Patent number: 12317540Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.Type: GrantFiled: February 16, 2022Date of Patent: May 27, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang
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Patent number: 12293952Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.Type: GrantFiled: May 9, 2024Date of Patent: May 6, 2025Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ho-Chuan Lin, Min-Han Chuang, Chia-Chu Lai
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Publication number: 20250140733Abstract: The present disclosure pertains to a die bonding structure. The die bonding structure includes a carrier substrate, a sintered layer, a nano-twinned layer, an adhesive layer and a chip. The sintered layer is located on the carrier substrate. The nano-twinned layer is located on the sintered layer, in which the surface of the nano-twinned layer has [111] crystal orientation with a density greater than 80%, in which the nano-twinned layer comprises parallel-arranged twin boundaries, the parallel-arranged twin boundaries comprise more than 40% [111] crystal orientation, and the spacing between the parallel-arranged twin boundaries is 10 to 100 nm. The adhesive layer is located on the nano-twinned layer. The chip is located on the adhesive layer.Type: ApplicationFiled: February 22, 2024Publication date: May 1, 2025Applicant: AG MATERIALS TECHNOLOGY CO., LTD.Inventors: Tung-Han CHUANG, Hsing-Hua TSAI, Chung-Hsin CHOU
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Publication number: 20250134745Abstract: An upper limb rehabilitation device includes a support mechanism, a flexion and extension rehabilitation mechanism, and a twist rehabilitation mechanism. The flexion and extension rehabilitation mechanism includes a sliding seat unit mounted on and movable forwardly and rearwardly relative to the support mechanism, and an arm rest seat mounted on the sliding seat unit for an arm of an upper limb of a patient to rest thereon. The arm rest seat is configured to be actuated by a flexion and extension movement of the arm of the upper limb of the patient to drive forward and rearward movement of the sliding seat unit relative to the support mechanism. The twist rehabilitation mechanism includes a handgrip unit mounted on the sliding seat unit and rotatable leftward and rightward relative to the same for a hand of the upper limb of the patient to grip.Type: ApplicationFiled: January 22, 2024Publication date: May 1, 2025Inventors: Hsiu-Yun HSU, Li-Chieh KUO, Kang-Chin YANG, Ping-Han CHUANG
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Publication number: 20250142883Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.Type: ApplicationFiled: November 1, 2023Publication date: May 1, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hung CHANG, Tsung-Han CHUANG, Fu-Cheng CHANG, Shih-Cheng CHEN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250126837Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.Type: ApplicationFiled: December 20, 2024Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250098219Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.Type: ApplicationFiled: February 15, 2024Publication date: March 20, 2025Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Tsung-Han CHUANG, Fu-Cheng CHANG, Wen-Ting LAN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG, Wang-Chun Huang, Shi-Syuan Huang
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Publication number: 20250098237Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.Type: ApplicationFiled: January 4, 2024Publication date: March 20, 2025Inventors: Jung-Hung Chang, Shih-Cheng Chen, Tsung-Han Chuang, Wen-Ting Lan, Chia-Cheng Tsai, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12243837Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.Type: GrantFiled: August 7, 2023Date of Patent: March 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang