Abstract: Disclosed is a microfluidic detection device including a circuit substrate and a transparent substrate. The circuit substrate is provided with at least one first light-emitting device used to emit a detection beam, a photodetector used to receive the detection beam and send out a sensing signal, and a control circuit electrically connected to the first light-emitting device and the photodetector. The transparent substrate overlaps the circuit substrate and is provided with a microfluidic channel and a light guide structure. The light guide structure has a light incident surface disposed corresponding to the first light-emitting device and a light exiting surface disposed corresponding to the photodetector. The light guide structure extends from each of the light incident surface and the light exiting surface to the microfluidic channel and is adapted to transmit the detection beam into and out of the microfluidic channel.

Abstract: A pixel array substrate includes a pixel driving circuit, a first insulating layer, a pad group, and an adjustment structure. The first insulating layer is disposed on the pixel driving circuit. The pad group is electrically connected to the pixel driving circuit. The adjustment structure is disposed on the first insulating layer and is electrically connected to the pad group. The adjustment structure is located between the pad group and the pixel driving circuit. The adjustment structure includes a first adjustment part and a second adjustment part. At least a part of the first adjustment part overlaps the pad group. The second adjustment part is disposed outside the first adjustment part and is staggered from the pad group. An absorptance of the first adjustment part to a laser is higher than an absorptance of the second adjustment part to the laser.

Abstract: A mask including patterned structures arranged sequentially along a predetermined direction and a peripheral area surrounding the patterned structures is provided. Each of the patterned structures includes an opening portion and a thinning portion surrounding the opening portion. The opening portion has through holes arranged in a matrix. An outline of the thinning portion has two side edges opposite to each other substantially parallel to the predetermined direction. The thinning portion is defined by an area demarked by the outline of the thinning portion and an outline of the opening portion. A thickness of the thinning portion is thinner than a thickness of the peripheral area.

Abstract: A mask including patterned structures arranged sequentially along a predetermined direction and a peripheral area surrounding the patterned structures is provided. Each of the patterned structures includes an opening portion and a thinning portion surrounding the opening portion. The opening portion has through holes arranged in a matrix. An outline of the thinning portion has two side edges opposite to each other substantially parallel to the predetermined direction. The thinning portion is defined by an area demarked by the outline of the thinning portion and an outline of the opening portion. A thickness of the thinning portion is thinner than a thickness of the peripheral area.

Abstract: A method of adhering an ethyl vinyl acetate copolymer or a derivative thereof layer to a thermoplastic elastomer layer includes providing the ethyl vinyl acetate copolymer or the derivative thereof layer; performing a first atmospheric environmental plasma treatment on a surface of the ethyl vinyl acetate copolymer or the derivative thereof layer to form a first modified surface; providing the thermoplastic elastomer layer; performing a second atmospheric environmental plasma treatment on a surface of the thermoplastic elastomer layer to form a second modified surface; forming an adhesive layer over the first modified surface, the second modified surface, or the first modified surface and the second modified surface; and adhering the first modified surface to the second modified surface through the adhesive layer.

Abstract: A LED package structure includes a substrate unit, a light-emitting unit and a package unit. The substrate unit includes two lead frames, and light-emitting unit including a LED chip electrically connected between the two lead frames. The package unit includes a light-transmitting package body enclosing the light-emitting unit and one part of each lead frame and a lens body integrated with the light-transmitting package body, and another part of each lead frame is exposed from the light-transmitting package body. Therefore, light beams generated by the LED chip pass through the lens body to project a cross light pattern on a plane, the cross light pattern has a concentrated cross light shape and a scattered light shape surrounding the concentrated cross light shape, the luminous intensity of the concentrated cross light shape is substantially the same and larger than the luminous intensity of the scattered light shape.

Abstract: A method is used to prevent unwanted electrical contacts between various electrically conducting surfaces and lines in a display panel due to an n+ a-Si residue and/or ITO debris. The method provides a clearing pattern including at least a cleared area in the passivation layer for preventing the residue or debris from locating at the cleared area. As such, if an n+ a-Si residue happens to be deposited under the passivation layer, the part of the residue located in the cleared area is removed by an a-Si selective etching process, for example. Furthermore, with the cleared area, ITO debris deposited on the section of the dielectric layer deposited on the signal line can be electrically isolated from the electrode.

Abstract: A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.

Abstract: A thin film transistor array substrate including a substrate, scan lines, data lines, thin film transistors, pixel electrodes, common lines and a patterned upper electrode is provided. The scan lines and the data lines are disposed over the substrate to define pixel areas. Each thin film transistor is disposed within one of the pixel areas and is driven by one of the scan lines and data lines. Each pixel electrode is disposed within one of the pixel areas and is electrically connected to one of the thin film transistors. Common lines are disposed over the substrate such that a portion area of each pixel electrode is located above one of the common lines. The pattern upper electrode includes sub-upper electrodes disposed between the pixel electrode and the common line. The sub-upper electrodes are electrically connected to the pixel electrodes for coupling with the common lines to form a storage capacitor.

Abstract: A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.

Abstract: An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units is provide. All of the scan lines, the data lines, the pixel units are disposed on the substrate. Each of the pixel units is electrically connected with the corresponding scan line and data line. In addition, at least a part of the pixel units further includes a plurality of active devices and a pixel electrode. The active devices are respectively electrically connected with the corresponding scan lines and data lines and the pixel unit is electrically connected with one of the active devices. In summary, each of the pixel units of the active matrix substrate provided by the invention includes more than one active device. When an active device is damaged under normal operation, another active device may be employed for repairing the pixel unit.

Abstract: A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.

Abstract: A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.

Abstract: A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.

Abstract: A thin film transistor array substrate including a substrate, scan lines, data lines, thin film transistors, pixel electrodes, common lines and a patterned upper electrode is provided. The scan lines and the data lines are disposed over the substrate to define pixel areas. Each thin film transistor is disposed within one of the pixel areas and is driven by one of the scan lines and data lines. Each pixel electrode is disposed within one of the pixel areas and is electrically connected to one of the thin film transistors. Common lines are disposed over the substrate such that a portion area of each pixel electrode is located above one of the common lines. The pattern upper electrode includes sub-upper electrodes disposed between the pixel electrode and the common line. The sub-upper electrodes are electrically connected to the pixel electrodes for coupling with the common lines to form a storage capacitor.

Abstract: An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.

Abstract: An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units is provide. All of the scan lines, the data lines, the pixel units are disposed on the substrate. Each of the pixel units is electrically connected with the corresponding scan line and data line. In addition, at least a part of the pixel units further includes a plurality of active devices and a pixel electrode. The active devices are respectively electrically connected with the corresponding scan lines and data lines and the pixel unit is electrically connected with one of the active devices. In summary, each of the pixel units of the active matrix substrate provided by the invention includes more than one active device. When an active device is damaged under normal operation, another active device may be employed for repairing the pixel unit.

Abstract: A method for repairing a storage capacitor on gate or a storage capacitor on common line is described. A portion of each pixel electrode is disposed above a scan line or a common line. An upper electrode is disposed between the pixel electrode and the corresponding scan line or the common line. The pixel electrode and the upper electrode are electrically connected. A defective capacitor is formed when a particle/defect is produced between the upper electrode and the common line or the scan line. The method of repairing the defective capacitor includes removing a portion of the pixel electrode corresponding to the upper electrode of a defective storage capacitor and electrically isolating the upper electrode and the corresponding pixel electrode of the defective storage capacitor. The upper electrode and the scan line or the common line of the defective capacitor are welded together.

Abstract: An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units is provide. All of the scan lines, the data lines, the pixel units are disposed on the substrate. Each of the pixel units is electrically connected with the corresponding scan line and data line. In addition, at least a part of the pixel units further includes a plurality of active units and a pixel electrode. The active devices are respectively electrically connected with the corresponding scan lines and data lines and the pixel unit is electrically connected with one of the active devices. In summary, each of the pixel units of the active matrix substrate provided by the invention includes more than one active device. When an active device is damaged under normal operation, another active device may be employed for repairing the pixel unit.

Abstract: A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.