Abstract: A host signal processing accelerator and method of using the same is provided in which certain signal processing tasks which are computing intensive but are contained in short lengths of code are downloaded from the host processor to the accelerator for processing. Signal processing tasks such as FIR (finite impulse response), IIR (infinite impulse response), and FFT/IFFT (fast Fourier transform/inverse fast Fourier transform) are sent from the host processor in machine code form to a double-buffered command memory for downloading onto the system bus. The task is loaded into a command buffer located on the accelerator, and is then passed to the accelerator's signal processor for execution. The results are sent to a status buffer on the host processor.

Abstract: A host signal processor (HSP) modem which includes procedures executed in response to interrupts has a CPU utilization control procedure which uses the numbers of clock cycles associated with modem tasks and the total number of clock cycles between interrupts to select a task for execution during the interrupts. The utilization control procedure changes or selects the task as required to automatically adjust the HSP modem for the available processing power and a desired maximum percentage utilization of a host computer. For example, the task can be selected to match the data transfer rate of the HSP modem with available processing power. The HSP modem is more robust and is operable in host computers having relatively low processing power. A user can change the maximum utilization of processing power used by the HSP modem so that more processing power is available for other purposes.