Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Abstract: Semiconductor structures and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first bottom source/drain feature and a second bottom source/drain feature disposed over a substrate, a plurality of bottom channel members extending between and in contact with the first bottom source/drain feature and the second bottom source/drain feature, a first bonding layer over the plurality of bottom channel members, a second bonding layer disposed directly on the first bonding layer, a first top source/drain feature disposed directly over the first bottom source/drain feature, a second top source/drain feature disposed directly over the second bottom source/drain feature, and a plurality of top channel members disposed over the second bonding layer and extending between and in contact with the first top source/drain feature and the second top source/drain feature.

Abstract: Bonding techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component and a second insulation layer on a second device component. A plasma activation process is performed to the first insulation layer and the second insulation layer. After the plasma activation process, an upper portion of the first insulation layer and the second insulation layer includes a plasma activated layer and a lower portion of the first insulation layer and the second insulation layer includes a barrier layer. The plasma activated layers of respective ones of the first insulation layer and the second insulation layer are bonded to form a stacked structure that includes the first device component over the second device component. The first insulation layer bonded to the second insulation layer forms an isolation structure between the first device component and the second device component.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

Abstract: The present disclosure provides a substrate bonding apparatus capable of temperature monitoring and temperature control. The substrate bonding apparatus comprises a fluid cooling module and a sensor module for detecting temperatures at multiple zones (e.g., two or more zones) within a substrate. The substrate bonding apparatus according to the present disclosure achieves temperature stabilization within the substrate. The substrate bonding apparatus further improves bonding process performance by reducing distortion residual, reducing bubbles on edges of the substrate, and reducing non-bonded area within the substrate.

Abstract: A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

Abstract: The present disclosure provides a substrate bonding apparatus capable of temperature monitoring and temperature control. The substrate bonding apparatus comprises a fluid cooling module and a sensor module for detecting temperatures at multiple zones (e.g., two or more zones) within a substrate. The substrate bonding apparatus according to the present disclosure achieves temperature stabilization within the substrate. The substrate bonding apparatus further improves bonding process performance by reducing distortion residual, reducing bubbles on edges of the substrate, and reducing non-bonded area within the substrate.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10?2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

Abstract: A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.