Abstract: A data storage device for reducing a firmware update time includes a non-volatile memory configured to store a firmware update image which will replace a current firmware image, a first volatile memory, and a processor configured to control an operation of the non-volatile memory and an operation of the first volatile memory. When a first code included in the current firmware image is executed by the processor, the first code generates data necessary for an operation of the data storage device and stores the data in the first volatile memory. When a second code included in the firmware update image is executed by the first code, the second code accesses and uses the data that has been stored in the first volatile memory.

Abstract: A data storage device for reducing a firmware update time includes a non-volatile memory configured to store a firmware update image which will replace a current firmware image, a first volatile memory, and a processor configured to control an operation of the non-volatile memory and an operation of the first volatile memory. When a first code included in the current firmware image is executed by the processor, the first code generates data necessary for an operation of the data storage device and stores the data in the first volatile memory. When a second code included in the firmware update image is executed by the first code, the second code accesses and uses the data that has been stored in the first volatile memory.

Abstract: A data storage device for reducing a firmware update time includes a non-volatile memory configured to store a firmware update image which will replace a current firmware image, a first volatile memory, and a processor configured to control an operation of the non-volatile memory and an operation of the first volatile memory. When a first code included in the current firmware image is executed by the processor, the first code generates data necessary for an operation of the data storage device and stores the data in the first volatile memory. When a second code included in the firmware update image is executed by the first code, the second code accesses and uses the data that has been stored in the first volatile memory.

Abstract: A nonvolatile memory system includes a memory controller for copying a mapping data group including logical-physical address mapping information regarding user data from a nonvolatile memory to a mapping information storage unit, and transmit size information regarding the mapping data group to a host. The host may receive size information regarding the mapping data group from the nonvolatile memory system, and determine the order of commands to be transmitted to the nonvolatile memory based on the size information regarding the mapping data group.

Abstract: A data storage device for reducing a firmware update time includes a non-volatile memory configured to store a firmware update image which will replace a current firmware image, a first volatile memory, and a processor configured to control an operation of the non-volatile memory and an operation of the first volatile memory. When a first code included in the current firmware image is executed by the processor, the first code generates data necessary for an operation of the data storage device and stores the data in the first volatile memory. When a second code included in the firmware update image is executed by the first code, the second code accesses and uses the data that has been stored in the first volatile memory.

Abstract: A nonvolatile memory system includes a memory controller for copying a mapping data group including logical-physical address mapping information regarding user data from a nonvolatile memory to a mapping information storage unit, and transmit size information regarding the mapping data group to a host. The host may receive size information regarding the mapping data group from the nonvolatile memory system, and determine the order of commands to be transmitted to the nonvolatile memory based on the size information regarding the mapping data group.

Abstract: Disclosed is a nonvolatile memory device which includes a nonvolatile memory having multi-level cell (MLC) storage; and a controller configured to control the nonvolatile memory, wherein if a logical address of write-requested data coincides with a logical address of data stored in the nonvolatile memory, the controller controls the nonvolatile memory to program the write-requested data prior to programming of a page sharing the same word line as a page including the data stored in the nonvolatile memory.