Patents by Inventor Han-Gon Ko
Han-Gon Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11423963Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.Type: GrantFiled: November 18, 2019Date of Patent: August 23, 2022Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Deog-Kyoon Jeong, Han-Gon Ko, Chan-Ho Kye, So-Yeong Shin
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Patent number: 11283655Abstract: Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver (20) generating waveform including data to be transmitted; and an FFE driver block (40) connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.Type: GrantFiled: February 12, 2021Date of Patent: March 22, 2022Assignee: Seoul National University R&DB FoundationInventors: Deog-Kyoon Jeong, KwangHoon Lee, Jung Hun Park, Han-Gon Ko, Soyeong Shin
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Patent number: 11121716Abstract: A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.Type: GrantFiled: September 21, 2020Date of Patent: September 14, 2021Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Soyeong Shin, Han-Gon Ko, Deog-Kyoon Jeong
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Publication number: 20210258194Abstract: Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver (20) generating waveform including data to be transmitted; and an FFE driver block (40) connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Deog-Kyoon JEONG, KwangHoon LEE, Jung Hun PARK, Han-Gon KO, Soyeong SHIN
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Publication number: 20210167783Abstract: A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.Type: ApplicationFiled: September 21, 2020Publication date: June 3, 2021Inventors: Soyeong SHIN, Han-Gon KO, Deog-Kyoon JEONG
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Patent number: 11005518Abstract: A transceiver circuit may include: a first NMOS transistor suitable for puffing up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.Type: GrantFiled: October 30, 2019Date of Patent: May 11, 2021Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Deog-Kyoon Jeong, Han-Gon Ko
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Publication number: 20200211605Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.Type: ApplicationFiled: November 18, 2019Publication date: July 2, 2020Inventors: Deog-Kyoon JEONG, Han-Gon KO, Chan-Ho KYE, So-Yeong SHIN
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Publication number: 20200067562Abstract: A transceiver circuit may include: a first NMOS transistor suitable for puffing up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.Type: ApplicationFiled: October 30, 2019Publication date: February 27, 2020Inventors: Deog-Kyoon JEONG, Han-Gon KO
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Patent number: 10498385Abstract: A transceiver circuit may include: a first NMOS transistor suitable for pulling up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.Type: GrantFiled: January 8, 2018Date of Patent: December 3, 2019Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Deog-Kyoon Jeong, Han-Gon Ko
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Publication number: 20180343028Abstract: A transceiver circuit may include: a first NMOS transistor suitable for pulling up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.Type: ApplicationFiled: January 8, 2018Publication date: November 29, 2018Inventors: Deog-Kyoon JEONG, Han-Gon KO
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Publication number: 20180226979Abstract: An injection locked phase locked loop includes an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated; a phase controller configured to generate a phase control signal according to a phase error signal; and an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.Type: ApplicationFiled: September 11, 2017Publication date: August 9, 2018Inventors: Sungwoo KIM, Han-Gon KO, Suhwan KIM, Deog-Kyoon JEONG
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Patent number: 10044359Abstract: An injection locked phase locked loop includes an injection locked oscillator configured to generate an oscillation signal according to an injection signal and to generate a replica signal by replicating the oscillation signal when the injection signal is deactivated; a phase controller configured to generate a phase control signal according to a phase error signal; and an error detector configured to generate the phase error signal by comparing a phase of the oscillation signal and a phase of the replica signal, and to control a phase difference between the oscillation signal and the replica signal according to the phase control signal.Type: GrantFiled: September 11, 2017Date of Patent: August 7, 2018Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Sungwoo Kim, Han-Gon Ko, Suhwan Kim, Deog-Kyoon Jeong