Patents by Inventor Han-Gu Kim

Han-Gu Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7465993
    Abstract: A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Lee, Han-Gu Kim, Jae-Hyok Ko
  • Patent number: 7417282
    Abstract: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Sung-Pil Jang, Han-Gu Kim, Chan-Hee Jeon
  • Publication number: 20080042206
    Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.
    Type: Application
    Filed: August 30, 2007
    Publication date: February 21, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han-gu Kim, Ki-tae Lee, Jae-hyok Ko, Woo-sub Kim, Sung-Pil Jang
  • Patent number: 7280329
    Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: October 9, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-gu Kim, Ki-tae Lee, Jae-hyok Ko, Woo-sub Kim, Sung-pil Jang
  • Publication number: 20070176241
    Abstract: A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.
    Type: Application
    Filed: January 18, 2007
    Publication date: August 2, 2007
    Inventors: Ki-Tae Lee, Han-Gu Kim, Jae-Hyok Ko
  • Publication number: 20070177329
    Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.
    Type: Application
    Filed: December 28, 2006
    Publication date: August 2, 2007
    Inventors: Kyoung-Sik Im, Han-Gu Kim, Jae-Hyok Ko, Il-Hun Son, Suk-Jin Kim
  • Patent number: 7243628
    Abstract: An apparatus for assembling a crankshaft-sprocket aligns a timing mark of a sprocket to a predetermined line of a crankshaft, and includes a slider for slidably moving an interior circumference surface of the sprocket to an exterior circumference surface of the crankshaft. A guider is disposed on an end portion of the crankshaft so as to guide the slider to the crankshaft. A first aligner is disposed on the slider so as to align the timing mark of the sprocket to a predetermined portion of the slider. A second aligner aligns the slider such that the timing mark aligned by the first aligner is positioned to the predetermined line of the crankshaft.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: July 17, 2007
    Assignee: Hyundai Motor Company
    Inventor: Han Gu Kim
  • Publication number: 20060175663
    Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.
    Type: Application
    Filed: August 11, 2005
    Publication date: August 10, 2006
    Inventors: Chan-hee Jeon, Han-gu Kim, Sung-pil Jang
  • Publication number: 20060124994
    Abstract: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.
    Type: Application
    Filed: November 2, 2005
    Publication date: June 15, 2006
    Inventors: Sung-Pil Jang, Han-Gu Kim, Chan-Hee Jeon
  • Patent number: 6981873
    Abstract: A dental implant includes a fixture and an abutment in a body, and a head for a compaction drill is configured for implanting such an implant. The implant includes an upper abutment portion on which a denture is fixed, a fixture portion implanted in the jawbone and forming single or double threads, and a settling portion formed between the abutment portion and the fixture portion. The invention improves the stability of the implant, improves stabilization of the bone tissue affixed to the implant, effectively seals the socket from its surroundings and facilitates bonding between implant and jawbone. This is achieved because of the early healing of tissue around the implant and the greater surface area in contact with surrounding tissue. As a result, an artificial crown may be coupled with the implant during the same surgery.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: January 3, 2006
    Inventors: Young-Wook Choi, Yong-Chang Choi, Shin-Koo Kim, Han-Gu Kim, Jai-Hyun Lee
  • Publication number: 20050100861
    Abstract: A dental implant includes a fixture and an abutment in a body, and a head for a compaction drill is configured for implanting such an implant. The implant includes an upper abutment portion on which a denture is fixed, a fixture portion implanted in the jawbone and forming single or double threads, and a settling portion formed between the abutment portion and the fixture portion. The invention improves the stability of the implant, improves stabilization of the bone tissue affixed to the implant, effectively seals the socket from its surroundings and facilitates bonding between implant and jawbone. This is achieved because of the early healing of tissue around the implant and the greater surface area in contact with surrounding tissue. As a result, an artificial crown may be coupled with the implant during the same surgery.
    Type: Application
    Filed: December 23, 2004
    Publication date: May 12, 2005
    Inventors: Young-Wook Choi, Yong-Chang Choi, Shin-Koo Kim, Han-Gu Kim, Jai-Hyun Lee
  • Publication number: 20050045955
    Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 3, 2005
    Inventors: Han-gu Kim, Ki-tae Lee, Jae-hyok Ko, Woo-sub Kim, Sung-pil Jang
  • Publication number: 20040219488
    Abstract: A dental implant, which includes a fixture and an abutment in a body, and the head for a compaction drill for implanting an implant are provided. The implant comprises an upper abutment portion on which a denture is fixed, a fixture portion implanted in the jawbone and forming single or double threads and a settling portion formed between the abutment portion and the fixture portion. The invention improves the stability of the implant exceedingly, improves stabilization of the bone tissue affixed to the implant, effectively seals the socket from its surroundings, and facilitates bonding between implant and jawbone. This is achieved because of the early healing of tissue around the implant and the greater surface area in contact with surrounding tissue. As a result, an artificial crown may be coupled with the implant during the same surgery.
    Type: Application
    Filed: June 6, 2003
    Publication date: November 4, 2004
    Inventors: Young-Wook Choi, Yong-Chang Choi, Shin-Koo Kim, Han-Gu Kim, Jai-Hyun Lee