Patents by Inventor Han Hsieh

Han Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176143
    Abstract: A head-mounted display, controlling method, and non-transitory computer readable storage medium thereof are provided. The head-mounted display determines a first posture among a plurality of postures based on a plurality of real-time images. The head-mounted display generates a first gesture among a plurality of gestures corresponding to a user according to a plurality of inertial measurement parameters corresponding to a first body part of the user. The head-mounted display generates a control signal corresponding to a first output event among a plurality of output events based on the first gesture and the first gesture.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Chao-Hsiang Lai, Cheng-Han Hsieh, Tzu-Wei Huang
  • Publication number: 20240166124
    Abstract: A light emitting device emitting an output light includes a light adjustment structure. A sub light is defined as the output light corresponding to an azimuth angle, a first value L1 is a sum of a luminance of the sub light corresponding to a polar angle from 115 to 125 degrees, a second value L2 is a sum of a luminance of the sub light corresponding to a polar angle from 95 to 105 degrees, a third value L3 is a sum of a luminance of the sub light corresponding to a polar angle from 75 to 85 degrees, a fourth value L4 is a sum of a luminance of the sub light corresponding to a polar angle from 55 to 65 degrees. The first value L1, the second value L2, the third value L3 and the fourth value L4 satisfy L3<L2, and 1.23?(L1*L3)/(L2*L4)?2.92.
    Type: Application
    Filed: October 22, 2023
    Publication date: May 23, 2024
    Applicant: InnoLux Corporation
    Inventors: Yu-Chia HUANG, Hong-Sheng HSIEH, Tsung-Han TSAI
  • Publication number: 20240167920
    Abstract: This disclosure presents a composition for tissue staining and 3D specimen optical clearing, along with a method of making biological material transparent and labeling it simultaneously. The composition includes an amide dye adjuvant, a RI-matching material, a permeating agent, a labeling material, a mixture homogeneity excipient, and a solvent with DMSO. The RI-matching material includes a contrast agent and sugar. The composition has a neutral or acidic pH. The method involves fixing a specimen with a fixative solution and immersing and incubating the specimen in the composition for permeation. This disclosure also presents a kit for rendering biological material transparent. The kit is helpful for experimental animal/human histological studies and cancer staging/tumor differentiation determination.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 23, 2024
    Applicant: JelloX Biotech Inc.
    Inventors: Yu-Han Hsieh, Yi-Wen Lin, YU-CHIEH LIN, YEN-YIN LIN
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240147718
    Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Patent number: 11971565
    Abstract: An absorption type near-infrared filter comprising a first multilayer film, a second multilayer film, and an absorption film, wherein in the ultraviolet band, the difference of between the wavelength with the transmittance at 80% of the absorbing film and the wavelength with the reflectivity at 80% of the first multilayer film falls in the range between 25 nm and 37 nm, the difference of between the wavelength with the transmittance at 50% of the absorbing film and the wavelength with the reflectivity at 50% of the first multilayer film falls in the range between 6 nm and 14 nm, and the difference of between the wavelength with the transmittance at 20% of the absorbing film and the wavelength with the reflectivity at 20% of the first multilayer film falls in the range between ?6 nm and 2.5 nm.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 30, 2024
    Assignees: PTOT (SUZHOU) INC., PLATINUM OPTICS TECHNOLOGY INC.
    Inventors: Chung-Han Lu, Hsiao-Ching Shen, Chun-Cheng Hsieh, Ming-Zhan Wang
  • Publication number: 20240134279
    Abstract: A photoresist includes a solvent, a polymer and an additive. The polymer is dissolved in the solvent, and the additive is dispersed in the solvent. The additive includes a double bond or includes an epoxy group. The additive has a surface tension different from a surface tension of the polymer.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240128149
    Abstract: Some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. The cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chieh HSIEH, Wei-Kong SHENG, Ke-Han SHEN, Yu-Jen LIEN
  • Publication number: 20240124163
    Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 18, 2024
    Applicant: National Cheng Kung University
    Inventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
  • Publication number: 20240128143
    Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.
    Type: Application
    Filed: February 1, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Hsieh, Yu-Jin Hu, Hua-Wei Tseng, An-Jhih Su, Der-Chyang Yeh
  • Publication number: 20240126123
    Abstract: This disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a first substrate, a second substrate, a first supporting member and a plurality of second supporting members. The first supporting member and the second supporting members are disposed between the first substrate and the second substrate. The first supporting member includes a first bottom surface and a first top surface. The second supporting member is disposed adjacent to the first supporting member and includes a second bottom surface and a second top surface. The difference between the radius of the first bottom surface and the radius of the first top surface is defined as a first radius bias. The difference between the radius of the second bottom surface and the radius of the second top surface is defined as a second radius bias. The first radius bias is greater than the second radius bias.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 18, 2024
    Applicant: InnoLux Corporation
    Inventors: Chiung-Chieh KUO, Chi-Han HSIEH, Hsiang-Wen HSUEH, Shu-Hung SHEN
  • Patent number: 11955439
    Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Publication number: 20240113142
    Abstract: An image sensor includes a group of sensor units, a color filter layer disposed within the group of sensor units, and a dielectric structure and a metasurface disposed corresponding to the color filter layer. The metasurface includes a plurality of peripheral nanoposts located at corners of the group of sensor units from top view, respectively, a central nanopost enclosed by the plurality of peripheral nanoposts, and a filling material laterally surrounding the plurality of peripheral nanoposts and the central nanopost. The central nanopost is offset from a center point of the group of sensor units by a distance from top view.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Po-Han FU, Wei-Ko WANG, Shih-Liang KU, Chin-Chuan HSIEH
  • Fan
    Patent number: 11946483
    Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
  • Publication number: 20240107023
    Abstract: A method of encoding video data includes determining an integer sample in a reference picture of the video data; determining, based on the integer sample, at least a first fractional sample and a second fractional sample, wherein the first fractional sample has a first fractional pel resolution, and the second fractional sample has a second fractional pel resolution different from the first fractional pel resolution; subsequent to determining both the first fractional sample and the second fractional sample, determining a first cost metric associated with the first fractional sample and a second cost metric associated with the second fractional sample; determining a reference block for a current block based on at least one of the first cost metric or the second cost metric; and encoding the current block based on the reference block.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Yu Han, Vladan Andrijanic, Wei-Jung Chien, Cheng-Teh Hsieh, Marta Karczewicz
  • Publication number: 20240096623
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer comprising an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing material and one or more selected from the group consisting of a photoacid generator, an actinic radiation absorbing additive including an iodine substituent, and a silicon-containing monomer having iodine or phenol group substituents. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.
    Type: Application
    Filed: March 17, 2023
    Publication date: March 21, 2024
    Inventors: Chieh-Hsin HSIEH, Wei-Han LAI, Ching-Yu CHANG
  • Publication number: 20240090216
    Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han LIN, Chih-Ren HSIEH, Ching-Wen CHAN