Patents by Inventor Han-Hsing Liu

Han-Hsing Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash memory structure and manufacturing method thereof
    Patent number: 6972455
    Abstract: A flash memory structure having high coupling ratio and the manufacturing method thereof are provided.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: December 6, 2005
    Assignee: Winbond Electronics Corporation
    Inventor: Han-Hsing Liu
  • Polycide gate stucture and manufacturing method thereof
    Publication number: 20050148120
    Abstract: A polycide gate structure and the manufacturing method thereof are provided. The manufacturing method includes the following steps of: (a) providing a substrate; (b) forming a polysilicon layer and a silicide layer upon the substrate separately; (c) removing a part of the silicide layer for defining a silicide structure having a side wall; (d) forming a protecting structure covering the side wall of the silicide structure; (e) removing the polysilicon layer not covered by the silicide structure and the protecting structure for obtaining a polysilicon structure having laterals; and (f) oxidating the polysilicon structure for forming an insulating structure on laterals of the polysilicon structure.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 7, 2005
    Applicant: Winbond Electronics Corporation
    Inventor: Han-Hsing Liu
  • Flash memory structure and manufacturing method thereof
    Publication number: 20040159878
    Abstract: A flash memory structure having high coupling ratio and the manufacturing method thereof are provided.
    Type: Application
    Filed: December 22, 2003
    Publication date: August 19, 2004
    Applicant: Winbond Electronics Corporation
    Inventor: Han-Hsing Liu
  • Double spacer salicide MOS process and device
    Patent number: 5824588
    Abstract: A double spacer salicide MOS device structure and a process for preparing such a device. The double spacer salicide device has a LDD structure. The first sidewall spacer disposed adjacent to the gate structure of the MOS device is higher than the gate. During the salicide process, the first sidewall spacer is used to effectively isolate the gate from the source/drain. The second sidewall spacer disposed adjacent to the first sidewall spacer is used to form the LDD structure.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: October 20, 1998
    Assignee: Winbond Electronics Corp.
    Inventor: Han-Hsing Liu