Patents by Inventor Han Jen
Han Jen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126002Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.Type: ApplicationFiled: October 2, 2023Publication date: April 18, 2024Applicant: Coretronic CorporationInventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
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Patent number: 11936877Abstract: A video decoder can be configured to determine that a current block in a current picture of the video data is coded in an affine prediction mode; determine one or more control-point motion vectors (CPMVs) for the current block; identify an initial prediction block for the current block in a reference picture using the one or more CPMVs; determine a current template for the current block in the current picture; and determine an initial reference template for the initial prediction block in the reference picture; and perform a motion vector refinement process to determine a modified prediction block based on a comparison of the current template to the initial reference template.Type: GrantFiled: April 7, 2022Date of Patent: March 19, 2024Assignee: QUALCOMM IncorporatedInventors: Chun-Chi Chen, Han Huang, Zhi Zhang, Yao-Jen Chang, Yan Zhang, Vadim Seregin, Marta Karczewicz
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Publication number: 20240077306Abstract: An image projector includes a light source capable of switchable emitting different patterns of light; and a beam shaper that shapes a light beam emitted by the light source, thereby generating a shaped pattern of light to be projected onto an object in a scene.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Yin-Tung Lu, Han-Yi Kuo, Shi-Jen Wu
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Patent number: 11924410Abstract: An example device for decoding video data includes one or more processors implemented in circuitry and configured to: generate an inter-prediction block for a current block of video data; generate an intra-prediction block for the current block of video data; generate a final prediction block for the current block of video data from the inter-prediction block and the intra-prediction block, including performing each of combined inter/intra prediction (CIIP) mode, overlapped block motion compensation (OBMC), and luma mapping with chroma scaling (LMCS) while generating the final prediction block; and decode the current block of video data using the final prediction block. To generate the final prediction block, the processors may perform LMCS on a first inter-prediction sub-block, combine the LMCS-mapped first inter-prediction sub-block with the intra-prediction block using CIIP, and perform OBMC between the first CIIP prediction block and a second inter-prediction sub-block.Type: GrantFiled: May 5, 2022Date of Patent: March 5, 2024Assignee: QUALCOMM IncorporatedInventors: Han Huang, Yao-Jen Chang, Vadim Seregin, Chun-Chi Chen, Marta Karczewicz
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Patent number: 11428986Abstract: A direct-type light source module including N-stage light sources and an optical sheet is provided. The optical sheet is disposed above the N-stage light sources, and an optical distance between the i-th-stage light source and the optical sheet is smaller than an optical distance between the i+1-th-stage light source and the optical sheet, where 1?i<N, and N is a positive integer greater than 1. A display device is also provided.Type: GrantFiled: August 2, 2021Date of Patent: August 30, 2022Assignee: Wistron CorporationInventors: Han-Jen Liang, Lei-Ken Hung, Ching-Hsuan Tsai, Wei-Chi Lin, Chih-Chou Chou
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Patent number: 11380673Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.Type: GrantFiled: November 30, 2020Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
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Publication number: 20210082907Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
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Publication number: 20200411506Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Lin Peng, Han-Jen Yang, Jam-Wem Lee, Li-Wei Chu
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Patent number: 10854595Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.Type: GrantFiled: December 13, 2018Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
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Patent number: 10790274Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.Type: GrantFiled: October 19, 2017Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ti Su, Wun-Jie Lin, Han-Jen Yang, Shui-Ming Cheng, Ming-Hsiang Song
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Patent number: 10777546Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.Type: GrantFiled: December 29, 2016Date of Patent: September 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Lin Peng, Han-Jen Yang, Jam-Wem Lee, Li-Wei Chu
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Patent number: 10600568Abstract: A capacitor includes a first electrode, a dielectric, and a second electrode. The first electrode is located on a dielectric layer. The dielectric covers the sidewall and the top surface of the first electrode. The second electrode covers the dielectric and the dielectric layer, wherein the orthographic projection area of the second electrode on the dielectric layer is greater than the orthographic projection area of the first electrode on the dielectric layer. The capacitor of the invention has good reliability.Type: GrantFiled: June 9, 2017Date of Patent: March 24, 2020Assignee: United Microelectronics Corp.Inventor: Po-Han Jen
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Patent number: 10546850Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.Type: GrantFiled: December 24, 2018Date of Patent: January 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
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Patent number: 10373966Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including an upper horizontal bar, a lower horizontal bar contiguous with the upper horizontal bar, and a step structure with a step height at which the two bars are contiguous, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the upper horizontal bar of each first poly-Si layer, and on the second silicide layer.Type: GrantFiled: September 13, 2016Date of Patent: August 6, 2019Assignee: United Microelectronics Corp.Inventors: Po-Han Jen, Chieh-Yu Tsai, Chun-Cheng Chiang
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Publication number: 20190148357Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.Type: ApplicationFiled: December 24, 2018Publication date: May 16, 2019Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
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Publication number: 20190131293Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.Type: ApplicationFiled: December 13, 2018Publication date: May 2, 2019Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
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Patent number: 10163894Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.Type: GrantFiled: February 12, 2018Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das
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Patent number: 10157905Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.Type: GrantFiled: August 7, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
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Publication number: 20180337000Abstract: A capacitor includes a first electrode, a dielectric, and a second electrode. The first electrode is located on a dielectric layer. The dielectric covers the sidewall and the top surface of the first electrode. The second electrode covers the dielectric and the dielectric layer, wherein the orthographic projection area of the second electrode on the dielectric layer is greater than the orthographic projection area of the first electrode on the dielectric layer. The capacitor of the invention has good reliability.Type: ApplicationFiled: June 9, 2017Publication date: November 22, 2018Applicant: United Microelectronics Corp.Inventor: Po-Han Jen
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Patent number: D998766Type: GrantFiled: January 4, 2022Date of Patent: September 12, 2023Inventors: Tianle Cheng, Hua Liao, Han-Jen Lin