Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: An electrostatic discharge (ESD) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. The extended drain region includes a number N of electrically floating doped regions and a number M of gate regions coupled to the second electrical node, where N and M are integers greater than 1 and N is equal to M. Each electrically floating doped region of the N number of floating doped regions alternates with each gate region of the M number of gate regions.

Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.