Patents by Inventor Han-Kyu Chi

Han-Kyu Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200145001
    Abstract: A semiconductor apparatus includes a termination voltage terminal, a first pin, a second pin, a first termination circuit and a second termination circuit. The first termination circuit is coupled between the termination voltage terminal and the first pin. The second termination circuit is coupled between the termination voltage terminal and a second pin. Resistance values of the first termination circuit and the second termination circuit may be determined on a basis of distances from the termination voltage terminal to the first pin and the second pin.
    Type: Application
    Filed: June 13, 2019
    Publication date: May 7, 2020
    Applicant: SK hynix Inc.
    Inventors: Jun Yong SONG, Han Kyu CHI
  • Patent number: 10637471
    Abstract: A semiconductor apparatus includes a termination voltage terminal, a first pin, a second pin, a first termination circuit and a second termination circuit. The first termination circuit is coupled between the termination voltage terminal and the first pin. The second termination circuit is coupled between the termination voltage terminal and a second pin. Resistance values of the first termination circuit and the second termination circuit may be determined on a basis of distances from the termination voltage terminal to the first pin and the second pin.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jun Yong Song, Han Kyu Chi
  • Patent number: 10573361
    Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Han Kyu Chi, Min Su Park
  • Publication number: 20190333553
    Abstract: A semiconductor device includes a control circuit configured to generate a data reset signal which is enabled in response to a reset signal and first and second transfer control signals which are sequentially enabled in synchronization with a divided clock in response to a read signal and a trigger circuit configured to drive a driving signal depending on a logic level of latch data in synchronization with delayed clocks in response to the first and second transfer control signals, the driving signal having a fixed logic level based on the data reset signal being enabled.
    Type: Application
    Filed: December 5, 2018
    Publication date: October 31, 2019
    Applicant: SK hynix Inc.
    Inventors: Geun Ho CHOI, Han Kyu CHI, Min Su PARK
  • Patent number: 10284396
    Abstract: A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 7, 2019
    Assignee: SK hynix Inc.
    Inventors: Jun Yong Song, Jeong Kyoum Kim, Hyung Soo Kim, Han Kyu Chi
  • Patent number: 10110266
    Abstract: A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing s
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 23, 2018
    Assignee: SK hynix Inc.
    Inventors: Jun Yong Song, Jeong Kyoum Kim, Hyung Soo Kim, Han Kyu Chi
  • Publication number: 20180262372
    Abstract: A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.
    Type: Application
    Filed: November 3, 2017
    Publication date: September 13, 2018
    Applicant: SK hynix Inc.
    Inventors: Jun Yong SONG, Jeong Kyoum KIM, Hyung Soo KIM, Han Kyu CHI
  • Publication number: 20180183474
    Abstract: A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing s
    Type: Application
    Filed: September 11, 2017
    Publication date: June 28, 2018
    Applicant: SK hynix Inc.
    Inventors: Jun Yong SONG, Jeong Kyoum KIM, Hyung Soo KIM, Han Kyu CHI
  • Publication number: 20180183630
    Abstract: A receiving circuit may include a decision feedback equalizer circuit and buffer. The buffer may be configured to receive an external signal and to generate an input signal. The decision feedback equalizer circuit may include a plurality of delay circuits, and may be configured to generate an internal signal based on the input signal, a strobe signal, and outputs of the plurality of delay circuits. The plurality of delay circuits may be reset based on whether or not the strobe signal has toggled or not between command signals.
    Type: Application
    Filed: July 6, 2017
    Publication date: June 28, 2018
    Applicant: SK hynix Inc.
    Inventors: Jeong Kyoum KIM, Jun Yong SONG, Han Kyu CHI
  • Patent number: 9887831
    Abstract: A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: February 6, 2018
    Assignee: SK Hynix Inc.
    Inventors: Woo-Yeol Shin, Myeong-Jae Park, Kyu-Young Kim, Han-Kyu Chi, Sung-Eun Lee, Kyung-Hoon Kim
  • Patent number: 9887691
    Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Myeong Jae Park, Kyung Hoon Kim, Woo Yeol Shin, Han Kyu Chi
  • Patent number: 9793901
    Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: October 17, 2017
    Assignee: SK Hynix Inc.
    Inventors: Han-Kyu Chi, Kyung-Hoon Kim, Myeong-Jae Park, Taek-Sang Song, Tae-Wook Kang
  • Publication number: 20170294899
    Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 12, 2017
    Applicant: SK hynix Inc.
    Inventors: Myeong Jae PARK, Kyung Hoon KIM, Woo Yeol SHIN, Han Kyu CHI
  • Patent number: 9787296
    Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Sung-Eun Lee, Kyung-Hoon Kim, Myeong-Jae Park, Woo-Yeol Shin, Han-Kyu Chi, Yong-Ju Kim
  • Publication number: 20170272063
    Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.
    Type: Application
    Filed: August 11, 2016
    Publication date: September 21, 2017
    Inventors: Sung-Eun LEE, Kyung-Hoon KIM, Myeong-Jae PARK, Woo-Yeol SHIN, Han-Kyu CHI, Yong-Ju KIM
  • Publication number: 20170237442
    Abstract: A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.
    Type: Application
    Filed: June 23, 2016
    Publication date: August 17, 2017
    Inventors: Kyung Hoon KIM, Myeong Jae PARK, Woo Yeol SHIN, Sung Eun LEE, Han Kyu CHI, Jae Won HAN
  • Publication number: 20170237550
    Abstract: A clock data recovery circuit may include: a phase comparison unit suitable for comparing input data with a phase of a multi-phase clock, and for generating an up/down signal corresponding to the comparison result; a filtering unit suitable for counting the up/down signal based on an upper threshold value and a lower threshold value, for setting, when an overflow occurs, the lower threshold value to an initial value for the count of the up/down signal, or when a underflow occurs, the upper threshold value to the initial value for the count of the up/down signal, and for generating a control code corresponding to one of the underflow and the overflow; and a phase rotating unit suitable for adjusting the phase of the multi-phase clock in response to the control code outputted from the filtering unit.
    Type: Application
    Filed: July 8, 2016
    Publication date: August 17, 2017
    Inventors: Woo-Yeol SHIN, Myeong-Jae PARK, Kyu-Young KIM, Han-Kyu CHI, Sung-Eun LEE, Kyung-Hoon KIM
  • Patent number: 9722583
    Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a periodic signal, the periodic signals periodically toggled in response to the command, output the data in response to the periodic signal, and discharge the charges of an internal node if the periodic signal is not toggled during a predetermined section.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 1, 2017
    Assignee: SK hynix Inc.
    Inventors: Myeong Jae Park, Kyung Hoon Kim, Woo Yeol Shin, Han Kyu Chi
  • Patent number: 9667261
    Abstract: An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: May 30, 2017
    Assignee: SK Hynix Inc.
    Inventors: Han-Kyu Chi, Taek-Sang Song
  • Publication number: 20170063384
    Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.
    Type: Application
    Filed: January 13, 2016
    Publication date: March 2, 2017
    Inventors: Han-Kyu CHI, Kyung-Hoon KIM, Myeong-Jae PARK, Taek-Sang SONG, Tae-Wook KANG