Abstract: The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

Abstract: A power module, includes a leadless frame substrate including a first metal layer and an insulating layer, wherein the first metal layer forms a circuit trace disposed on the insulating layer and the first metal layer has an extension structure extending out of the insulating layer to serve as an output terminal; at least one semiconductor power device disposed on the first metal layer; a current detector disposed on the output terminal; and a molding compound, completely covering the first metal layer on the insulating layer of the leadless frame substrate and the at least one semiconductor power device, and partially covering the output terminal so that the current detector is completely disposed outside the molding compound.

Abstract: A radiative heat dissipation casing, including: an enclosure, which including a radiative heat dissipation unit whose material composition includes an aluminum oxide-boron nitride-fullerene composite material, for an enhanced thermal radiation dissipation; a heat generation element, disposed inside the enclosure; and an internal heat transfer bridge, disposed between the heat generation element and the enclosure, wherein the waste heat from the heat generation element is transferred via the internal heat transfer bridge to the radiative heat dissipation unit and then radiated to the outside of the enclosure.

Abstract: A synchronizing hinge includes a rotating module and a bracket plate unit. The rotating module includes two support units pivotably mounted to a base seat. Each support unit has a first support piece, a second support piece pivotably connected with the first support piece, and a moving axle extending through the first support piece and an arcuate slot of the second support piece and movably received in a moving slot of the base seat. The bracket plate unit includes two first bracket plates securely connected with the first support piece, and two second bracket plates securely connected with the second support piece. The support units and the bracket plate unit are rotatable between an initial position where the first bracket plates are flush with the second bracket plates, and a terminal position where the first bracket plates are inclined relative to the second bracket plates by an inclined angle.

Abstract: A semiconductor device comprising a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed radially outwards of at least one radially outer surface of the source and the drain in a second direction perpendicular to the first direction, the channel layer extending in the first direction. A memory layer is disposed on a radially outer surface of the channel layer in the second direction and extending in the first direction. A contact structure is interposed between the channel layer and at least a portion of the source and/or the drain, the contact structure having a lower resistance than the channel layer.

Abstract: A power semiconductor device, including a terminal base, is provided. The terminal base has a first end and a second end opposite to each other. The first end has a first flange expanding outward. The first flange is welded to a pad of a substrate by a solder. An included angle between an extension direction of the first flange and a length direction of the terminal base is greater than 90 degrees.

Abstract: Disclosed are a cement-based battery and a method for manufacturing thereof. The cement-based battery includes a waterproof structure, a battery body, a positive electrode, a negative electrode, and an electrolyte solution. The waterproof structure is provided with an accommodating cavity. The battery body is disposed in the accommodating cavity, and includes a cement-based body, which is obtained by curing a solid-liquid mixture, wherein the solid-liquid mixture includes cement, a first porous material, and a first effective microorganism aqueous solution. The positive electrode and the negative electrode are connected to the battery body respectively and extend out of the waterproof structure. The electrolyte solution is disposed in the accommodating cavity. Therefore, the cement-based battery can be applied to a cement building as an energy storage battery to provide power at night, during power outages or during emergencies.

Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. A bit line structure and a trench adjacent to the bit line structure are provided, wherein a first spacer is disposed on a sidewall and a top surface of the bit line structure, and a second spacer is disposed on a sidewall and a top surface of the first spacer. A photoresist layer is formed in the trench, wherein the photoresist layer has a height that is smaller than a depth of the trench. A portion of the second spacer is removed, wherein the etched second spacer has a height that is substantially equal to the height of the photoresist layer. The photoresist layer is removed. A third spacer is formed on a sidewall of the etched second spacer, wherein the third spacer covers a top surface of the etched second spacer.

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate including an element isolation structure defining first to third active regions and first to third elements respectively in the first to third active region. The first element includes a first gate dielectric layer embedded in the first active region of the substrate and isolation structures embedded in the substrate at opposite sides of the first gate dielectric layer. Bottom surfaces of the isolation structures include first portions at the same level as a bottom surface of the element isolation structure and second portions being oblique with respective to the first portions.

Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

Abstract: A memory device includes a first memory cell. The first memory cell includes: a first conductor structure extending along a lateral direction; a first memory film comprising a first portion wrapping around a first portion of the first conductor structure; and a first semiconductor film wrapping around the first portion of the first memory film. A second conductor structure extends along a vertical direction and is coupled to a first end portion of the first semiconductor film along the lateral direction. A third conductor structure extends along the vertical direction and is coupled to a second end portion of the first semiconductor film along the lateral direction.

Abstract: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.

Abstract: A semiconductor device, comprises a source structure comprising an active source portion, an inactive source portion spaced apart from the active source portion in a vertical direction, and a first dielectric structure interposed between the active source portion and the inactive source portion. A drain structure is spaced apart from the source structure in a first direction. A channel layer is disposed on outer surfaces of the source and the drain structures. A memory layer is disposed on an outer surface of the channel layer so as to wrap around the channel layer. At least one gate layer is in electrical communication with the active source portion.

Abstract: An optical device is provided. The optical device includes a substrate and a plurality of optical structures. The substrate includes a plurality of photoelectric conversion elements. The optical structures are disposed above the substrate. Each optical structure corresponds to one photoelectric conversion element. Each optical structure includes a first portion and a second portion. The first portion has a first glass transition temperature. The second portion has a second glass transition temperature. The second portion guides the incident light into the photoelectric conversion element. The first glass transition temperature is higher than the second glass transition temperature.

Abstract: A memory device includes a first signal line, a second signal line, a first memory cell, a second memory cell, a third memory cell and a fourth memory cell. The first memory cell is coupled to the first signal line. The second memory cell has a first terminal coupled to the first signal line through the first memory cell and a second terminal coupled to the second signal line. The third memory cell is coupled to the first signal line. The fourth memory cell is coupled to the first signal line through the third memory cell, wherein a parasitic capacitance of the fourth memory cell is isolated from the second memory cell through the third memory cell.