Patents by Inventor Han-Ming Hsieh

Han-Ming Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200387916
    Abstract: An intelligent Volume Profile charting device and method thereof for charting a tradable object are provided. A price-and-volume displaying module displays a level bar chart segmented to a plurality of volume bars corresponding to a plurality of price intervals. A featured-price-and-volume level module quantizes the featured prices to full-length level bar and quantizes the non-featured prices to zero-length level bars. A combining-and-generating module combines the full-length level bars and the zero-length level bars into at least one full volume block and at least one zero volume block. Investors could invest tradable objects more efficiently and effectively based on intelligent charts and calculations of entry point, exit point and expected return.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventor: HAN-MING HSIEH
  • Publication number: 20190147535
    Abstract: A trade data processing device for financial instruments having a financial information receiving module, a price-and-volume displaying module displaying multiple price-and-volume information messages of financial information; a customized combination module generating multiple information options and allowing a user to select and generate combination information message, the featured-price-and-volume level module defining a featured price to generate multiple featured-price-and-volume level information messages to the combining-and-generating module according to the volume-defining level information message of the combination information message such that the multiple featured prices level bars are combined to form a featured-price-and-volume block, a featured-price-and-volume block information message is generated to the information displaying module to generate a comprehensive-featured price-and-volume block chart. The trade data processing device effectively assists an investor to invest.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 16, 2019
    Inventor: HAN-MING HSIEH
  • Patent number: 9442391
    Abstract: One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ming Hsieh, Li-Shiuan Chen, Chung-Hao Chang, Li-Kong Turn
  • Publication number: 20140278213
    Abstract: One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.
    Type: Application
    Filed: July 16, 2013
    Publication date: September 18, 2014
    Inventors: Han-Ming Hsieh, Li-Shiuan Chen, Chung-Hao Chang, Li-Kong Turn