Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

Abstract: A grill pan includes a flat portion and two slanting portions. The slanting portions are connected to each side of the flat portion respectively. Each of the slanting portions is formed with a spout positioned opposite to where the flat portion and the slanting portion meet. The slanting portions are slightly higher than the flat portion to divide a cooking area for low-fat food and a cooking area for high-fat food, and the slanting portions slope downward from the flat portion to allow any fluid on the cooking area for high-fat food to flow toward the spout instead of the cooking area for low-fat food during cooking.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A method and apparatus for etchback profile control. The method includes performing a first etch through a first dielectric layer to form a first via and a second dielectric layer, filling the first via with a BARC material to form a first BARC layer, and performing a second etch on the first BARC layer to form a second BARC layer. The second etch has a first etch rate in a first peripheral region of the second BARC layer and a second etch rate in a first central region of the second BARC layer. The first peripheral region is located around a sidewall of the first via, and the first central region is located around a center of the first via. The first etch rate is larger than the second etch rate, and the first peripheral region is located higher than the first central region. A first top surface of the second BARC layer has substantially a first convex shape. Additionally, the method includes performing a third etch through a second dielectric layer to form a trench and a third BARC layer.

Abstract: A method and apparatus are described for removing an initial gas from a gas-filled enclosure between the mask-protective device, such as a pellicle, and the patterned mask, such as a reticle, and adding a purge gas with a different composition. The gas-filled enclosure includes a vent for adding the purge gas to the chamber and removing the initial gas from the chamber. Adding and removing may be accomplished by using pressure, diffusion, vacuum, or other means.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A method for providing uniformity in plasma-assisted material processes. A shielding plate is implemented within a plasma chamber above a substrate. The dimensions, geometry, and location of the shielding plate are optimized to generate a desired ion flux in a plasma-assisted material process conducted in a plasma chamber.

Abstract: A method and apparatus for etchback profile control. The method includes performing a first etch through a first dielectric layer to form a first via and a second dielectric layer, filling the first via with a BARC material to form a first BARC layer, and performing a second etch on the first BARC layer to form a second BARC layer. The second etch has a first etch rate in a first peripheral region of the second BARC layer and a second etch rate in a first central region of the second BARC layer. The first peripheral region is located around a sidewall of the first via, and the first central region is located around a center of the first via. The first etch rate is larger than the second etch rate, and the first peripheral region is located higher than the first central region. A first top surface of the second BARC layer has substantially a first convex shape. Additionally, the method includes performing a third etch through a second dielectric layer to form a trench and a third BARC layer.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and laying a metallic thick film on the surface of the transparent conductive hetero-junction for wiring process in the later fabrication operation. Thus through the electron and hole tunneling effect in the ion diffusion process the Fermi level of the hetero-junction may be improved to form an ohmic contact electrode.

Abstract: A method for manufacturing gallium nitride based transparent conductive oxidized film ohmic electrodes includes forming a transparent conductive film on a GaN layer, forming a transparent conductive hetero-junction of opposing electrical characteristics on a transparent conductive film on the surface of the GaN layer through an ion diffusion process, and laying a metallic thick film on the surface of the transparent conductive hetero-junction for wiring process in the later fabrication operation. Thus through the electron and hole tunneling effect in the ion diffusion process the Fermi level of the hetero-junction may be improved to form an ohmic contact electrode.

Abstract: An apparatus comprising a plasma chamber containing a plasma for a plasma-assisted material process upon a substrate; a shielding plate within the plasma chamber to actively direct ion flux to desired areas of the substrate; and a supporting structure to support the shielding plate within the chamber is disclosed.

Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.

Abstract: A method and apparatus are described for removing an initial gas from a gas-filled enclosure between the mask-protective device, such as a pellicle, and the patterned mask, such as a reticle, and adding a purge gas with a different composition. The gas-filled enclosure includes a vent for adding the purge gas to the chamber and removing the initial gas from the chamber. Adding and removing may be accomplished by using pressure, diffusion, vacuum, or other means.

Abstract: Plasma etching is controlled utilizing two etchant gases to form a plasma so as to obtain controlled (e.g., uniform) etch rate across a wafer. One etchant gas forms appositive plasma, which is the dominant plasma. The other etchant gas forms a negative plasma, which is the secondary plasma. The ratio of dominant plasma to the secondary plasma can be adjusted such that ion densities are uniform across the wafer, resulting in uniform etch rate over the wafer.