Abstract: The present invention relates to an emergency escape breathing device for use in a fire ground, provided as an emergency life-saving apparatus and comprising an exhalation valve and a suction valve configured inside a main body. In addition, a biting piece is connected on the main body for biting by the mouth of a person, and an extension tube is connected to the main body for breathing clean air from the outside. Through the interactive operation of the exhalation valve and the suction valve provided by the present invention, the user can breathe smoothly and avoid repeated intake of carbon dioxide exhaust gas.

Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: An axle securing device for securing a polygonal axle and a roller secured thereto is provided. The axle securing device includes a bracket, an elastic buckle, and a first bolt. The bracket includes a clamping part for clamping the polygonal axle, a securing part, and two elongated arms connected between the clamping part and the securing part. The first bolt is inserted through the elastic buckle and the securing part to secure the elastic buckle on the bracket. The two elongated arms are held between two elastic arms of the elastic buckle, wherein the two elastic arms respectively apply clamping forces inwardly to the two elongated arms, and the clamping part is driven by the two elastic arms to constrict inwardly and thus restricting a movement of the polygonal axle. Another axle securing device is also provided.

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

Abstract: Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.

Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Abstract: A method of coating a surface of a metal structure in situ comprises the steps of applying an liquidous under coating of a modified polyvinylidene fluoride (PVDF) or polyvinylidene difluoride (PVDF) material in an air dryable solution, and then applying a liquidous over coating of a modified polyvinylidene fluoride (PVDF) or polyvinylidene difluoride (PVDF) material in an air dryable solution. The under coating has: a PVDF or a PVDF co-polymer or a combination thereof of less than about 75% blended with at least about 25% compatible acrylic and/or other compatible polymer; and the PVDF or PVDF co-polymer or blend thereof has a particular PVDF molecular structure and a polymer crystallinity. The over coating has: a PVDF or a PVDF co-polymer or a blend thereof that is fluorinated to at least about 70% and at least about 70% PVDF molecular structure.

Abstract: A method of coating a surface of a concrete structure in situ, which comprises the step of applying to the surface of the concrete of the concrete structure a liquidous coating of a modified polyvinylidene fluoride (PVDF) or polyvinylidene difluoride (PVDF) material in an air dryable solution comprising: a PVDF or a PVDF co-polymer or a combination of PVDF and PVDF copolymer to form a blend with a compatible acrylic and/or other compatible polymer that is fluorinated to between about 30% to about 75% by weight excluding any solvent; the PVDF or PVDF co-polymer or blend thereof having at least about 45% PVDF molecular structure by weight when dried; the PVDF or PVDF co-polymer having a polymer crystallinity of at least about 30% by weight; and a solvent.

Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to apply a program voltage to selected ones of the word lines while applying pass voltages to unselected ones of the word lines and ramp down both the selected ones of the plurality of word lines and the unselected ones of the word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply a targeted word line bias to each of the word lines during the verify phase. The control means is also configured to adjust the recovery voltage based on the targeted word line bias applied to each of the plurality of word lines during the verify phase.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.