Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Abstract: A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.

Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

Abstract: A semiconductor package includes a die, a passivation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The passivation layer is disposed on the die. The first electrical conductive vias and the second electrical conductive vias extend through the passivation layer and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the passivation layer. Each of the thermal conductive vias is spaced apart from the first and second electrical conductive vias. The connecting pattern is disposed on the passivation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.

Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Abstract: The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device. The semiconductor device structure includes a second conductive shielding layer under the first device. The first device is between the first conductive shielding layer and the second conductive shielding layer, and the second conductive shielding layer has a plurality of second openings.

Abstract: An integrated circuit (IC) die for electromagnetic band gap (EBG) noise suppression is provided. A power mesh and a ground mesh are stacked within a back end of line (BEOL) region overlying a semiconductor substrate, and an inductor is arranged over the power and ground meshes. The inductor comprises a plurality of inductor segments stacked upon one another and connected end to end to define a length of the inductor. A capacitor underlies the power and ground meshes, and is connected in series with the inductor. Respective terminals of the capacitor and the inductor are respectively coupled to the power and ground meshes. A method for manufacturing the IC die is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.

Abstract: Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.

Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.