Abstract: A time division multiplexing (TDM) method and apparatus for interfacing data from communication channels to a TDM bus. The TDM arrangement uses a shift register to control a tri-state buffer. The shift register regulates the tri-state buffer based on a data bit pattern loaded into the shift register. The data bit pattern corresponds to the status of the individual channels. Each channel is assigned a bit which indicates whether the channel is active or inactive. As the shift register shifts out data, the tri-state buffer allows data to flow onto the TDM bus when a bit indicating an active channel is present and insulates the TDM bus from the communication channels when a bit representing an inactive channel is present. A processor is used to control the interrelationship of the multiple communication channels and to generate the status bits to be loaded into the shift register. The processor fills the shift register through the use of a storage register.

Abstract: A time division multiplexing (TDM) method and apparatus for interfacing data channels with a TDM bus. The TDM interface uses a processor and a channel coordinator circuit to indicate which data channels are active, and to assign which TDM transmit channels and which TDM receive channels will correspond to the active data channels. The processor controls the flow of data by using a channel coordinator circuit which controls multiple shift registers. The multiple shift registers control the flow of data between the active channels and the TDM bus. Multiple storage registers are used to buffer the data flowing between the active channels and the shift registers.

Abstract: Disclosed is a method and apparatus for accomplishing high speed multiplication of binary numbers using a single clock cycle to achieve the same computational power provided by the multiple clock cycle shift register configurations or the asynchronous multistate logic configurations of the prior art. “Virtual shifts” are achieved by allocating one or more positions, within a register storing the partial products, as place holders, typically zeroes. These place holders can be inserted in a single clock cycle and do not require the multi-staged shift register configurations of the prior art.