Patents by Inventor Han-Rei Ma

Han-Rei Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130267067
    Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 10, 2013
    Inventors: Peter Wung Lee, Han-Rei Ma, Fu-Chang Hsu
  • Patent number: 8455923
    Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 4, 2013
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Han-Rei Ma, Fu-Chang Hsu
  • Patent number: 8237212
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: August 7, 2012
    Assignee: Abedneja Assetts AG L.L.C.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Publication number: 20120001233
    Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Inventors: Peter Wung Lee, Han-Rei Ma, Fu-Chang Hsu
  • Publication number: 20110170357
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Applicant: ABEDNEJA ASSETS AG L.L.C.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Patent number: 7915092
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 29, 2011
    Assignee: Abedneja Assets AG L.L.C.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Patent number: 7636252
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: December 22, 2009
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Publication number: 20080247230
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Application
    Filed: July 7, 2006
    Publication date: October 9, 2008
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Patent number: 7372736
    Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: May 13, 2008
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Publication number: 20080096327
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Application
    Filed: December 12, 2007
    Publication date: April 24, 2008
    Inventors: Peter Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Patent number: 7349257
    Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: March 25, 2008
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Patent number: 7339824
    Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: March 4, 2008
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Patent number: 7324384
    Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 29, 2008
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu
  • Patent number: 7289366
    Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 30, 2007
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Patent number: 7283401
    Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: October 16, 2007
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Publication number: 20070133341
    Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 14, 2007
    Inventors: Peter Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Publication number: 20070133289
    Abstract: The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. The devices of the present invention also include a high voltage PMOS placed on top of a deep N-well and NMOS placed above a triple P-well inside the deep N-well in the peripheral area to pass both positive and negative high voltage of around +20V and ?20V to the cell area. In one embodiment, the cell array, source lines and bit lines are all placed on top of the P-substrate without a deep N-well or Triple P-well. In other embodiments, the cell array, source lines and bit lines are placed on top of the deep N-well and triple P-well.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 14, 2007
    Inventors: Han-Rei Ma, Fu-Chang Hsu, Peter Lee, Xiang Hong
  • Publication number: 20070076480
    Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
    Type: Application
    Filed: December 4, 2006
    Publication date: April 5, 2007
    Inventors: Peter Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Publication number: 20070047302
    Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.
    Type: Application
    Filed: March 28, 2006
    Publication date: March 1, 2007
    Inventors: Peter Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
  • Patent number: 7154783
    Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: December 26, 2006
    Assignee: APlus Flash Technology, Inc.
    Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma