Patents by Inventor Han Seong Kim
Han Seong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240078710Abstract: Disclosed herein are a method, an apparatus and a storage medium for encoding/decoding using a transform-based feature map. An optimal basis vector is extracted from one or more feature maps, and a transform coefficient is acquired through a transform using the basis vector. The basis vector and the transform coefficient may be transmitted through a bitstream. In an embodiment, one or more feature maps are reconstructed using the basis vector and the transform coefficient, which are decoded from the bitstream.Type: ApplicationFiled: September 1, 2023Publication date: March 7, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Youn-Hee KIM, Jooyoung LEE, Se-Yoon JEONG, Jin-Soo CHOI, Dong-Gyu SIM, Na-Seong KWON, Seung-Jin PARK, Min-Hun LEE, Han-Sol CHOI
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Publication number: 20240066707Abstract: An apparatus for automatically fastening a chemical coupler to a connector of an automatic clean quick coupler (ACQC) system, includes a main body, a multi-degree of freedom (DOF) robot arm on the main body, a gripper on the multi-DOF robot arm that is configured to grip the chemical coupler, a vision sensor on the multi-DOF robot arm, and a controller connected to the gripper, the multi-DOF robot arm, and the vision sensor. The controller uses information about an environment surrounding the multi-DOF robot arm acquired by the vision sensor, to control an operation of the multi-DOF robot arm and an operation of the gripper.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Applicants: SAMSUNG ELECTRONICS CO., LTD., Industry-Academic Cooperation Foundation of Kyungnam UniversityInventors: Shibaek PARK, Han Sung KIM, Jooha MAENG, Youngsuk PARK, Gi Seong KIM, Sung Hun JEONG
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Patent number: 11881430Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.Type: GrantFiled: May 27, 2022Date of Patent: January 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Jin Kang, Jong Min Baek, Woo Kyung You, Kyu-Hee Han, Han Seong Kim, Jang Ho Lee, Sang Shin Jang
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Publication number: 20220285207Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.Type: ApplicationFiled: May 27, 2022Publication date: September 8, 2022Inventors: Sung Jin KANG, Jong Min BAEK, Woo Kyung YOU, Kyu-Hee HAN, Han Seong KIM, Jang Ho LEE, Sang Shin JANG
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Patent number: 11434478Abstract: The present disclosure provides novel Cas12a proteins, which cleave target nucleic acids and methods of use thereof.Type: GrantFiled: February 9, 2021Date of Patent: September 6, 2022Assignees: GFLAS LIFE SCIENCES, INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Sunghwa Choe, Jongjin Park, Ji Young Yoon, Han Seong Kim, Dong Wook Kim
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Patent number: 11348827Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.Type: GrantFiled: February 24, 2020Date of Patent: May 31, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Jin Kang, Jong Min Baek, Woo Kyung You, Kyu-Hee Han, Han Seong Kim, Jang Ho Lee, Sang Shin Jang
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Publication number: 20210292722Abstract: A novel CRISPR-associated protein and a use thereof are disclosed. A protein of the amino acid sequence of SEQ ID NO: 1 or SEQ ID NO: 3 exhibits the activity of endonucleases, which recognize and cleave an intracellular nucleic acid sequence linked to a guide RNA. Therefore, a novel CRISPR-associated protein can be used as a different nuclease for genome editing, in a CRISPR-Cas system.Type: ApplicationFiled: August 9, 2019Publication date: September 23, 2021Applicants: G+FLAS LIFE SCIENCES, SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Sunghwa CHOE, Han Seong KIM, Dong Wook KIM, Jongjin PARK, Jiyoung YOON
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Publication number: 20210222140Abstract: The present disclosure provides novel Cas12a proteins, which cleave target nucleic acids and methods of use thereof.Type: ApplicationFiled: February 9, 2021Publication date: July 22, 2021Inventors: Sunghwa CHOE, Jongjin PARK, Jiyoung YOON, Han Seong KIM, Dong Wook KIM
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Publication number: 20210020497Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.Type: ApplicationFiled: February 24, 2020Publication date: January 21, 2021Inventors: Sung Jin KANG, Jong Min BAEK, Woo Kyung YOU, Kyu-Hee HAN, Han Seong KIM, Jang Ho LEE, Sang Shin JANG
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Patent number: 10804145Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.Type: GrantFiled: August 20, 2019Date of Patent: October 13, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong Gil Kim, Han Seong Kim, Jong Min Baek, Ji Young Kim, Sung Bin Park, Deok Young Jung, Kyu Hee Han
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Publication number: 20200227314Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.Type: ApplicationFiled: August 20, 2019Publication date: July 16, 2020Inventors: Yeong Gil Kim, Han Seong Kim, Jong Min Baek, Ji Young Kim, Sung Bin Park, Deok Young Jung, Kyu Hee Han
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Patent number: 6117765Abstract: A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a plurality of insulating layers, interposed vertically between the plurality of metal layers. A metal wiring pattern is formed on each of the plurality of metal layers. The wiring patterns are separated by insulating spaces, and the insulating spaces in each of the plurality of metal layers are vertically shifted with regard to the neighboring one of the plurality of metal layers.Type: GrantFiled: September 7, 1999Date of Patent: September 12, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Han Seong Kim, Young Soo Jeon, Ho Sik Kim, Gi Ho Seo
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Patent number: 6074930Abstract: A method for forming trench isolation in the silicon substrate is disclosed. This method allows for an improved bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After a trench is formed, sidewall silicon dioxide is grown on the sidewall of the trench by a first oxidation process. Then, PE-TEOS is deposited on the silicon substrate and the sidewall of the trench. The PE-TEOS layer around the entrance of the trench is then etched back using argon gas. The second oxidation process or the first annealing proceeds to enhance the bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After the second oxidation process or the annealing, the trench is filled with O.sub.3 -TEOS, and then PE-TEOS is deposited over the O.sub.3 -TEOS layer. Finally, the second annealing process follows.Type: GrantFiled: September 17, 1998Date of Patent: June 13, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung Hawn Cho, Han Seong Kim, Chan Sik Park, Won Soon Lee
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Patent number: 5998872Abstract: A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a plurality of insulating layers, interposed vertically between the plurality of metal layers. A metal wiring pattern is formed on each of the plurality of metal layers. The wiring patterns are separated by insulating spaces, and the insulating spaces in each of the plurality of metal layers are vertically shifted with regard to the neighboring one of the plurality of metal layers.Type: GrantFiled: August 21, 1998Date of Patent: December 7, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Han Seong Kim, Young Soo Jeon, Ho Sik Kim, Gi Ho Seo