Abstract: Provided is a power chip integration module including: a first semiconductor chip; a second semiconductor chip; a wiring layer on an upper surface or a lower surface of the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip and the second semiconductor chip; an internal electrode extending from an internal electrode pad on an upper surface of at least one of the wiring layer, the first semiconductor chip, the second semiconductor chip, and combinations thereof to an external solder pad formed on an installation surface of the first semiconductor chip and the second semiconductor chip; and a first molding member in a shape to surround at least a portion of the first semiconductor chip, the second semiconductor chip, and the internal electrode.

Abstract: Provided is a power chip integration module including: a first semiconductor chip; a second semiconductor chip; a wiring layer on an upper surface or a lower surface of the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip and the second semiconductor chip; an internal electrode extending from an internal electrode pad on an upper surface of at least one of the wiring layer, the first semiconductor chip, the second semiconductor chip, and combinations thereof to an external solder pad formed on an installation surface of the first semiconductor chip and the second semiconductor chip; and a first molding member in a shape to surround at least a portion of the first semiconductor chip, the second semiconductor chip, and the internal electrode.

Abstract: The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate.

Abstract: Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.

Abstract: Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to bc separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type.

Abstract: Provided is a power semiconductor device comprising a pair of gate electrodes respectively disposed in a first trench and a second trench spaced apart from each other in a substrate; a body region having a first conductivity type disposed between the first trench and the second trench; a pair of floating regions having a first conductivity type spaced apart from each other and surrounding a bottom surface and at least one side surface of the first trench and the second trench, respectively; and a drift region having a second conductivity type which extends from below the pair of floating regions through a region between the pair of floating regions to the body region, wherein, in the drift region, the doping concentration of a second conductivity type between the pair of floating regions is higher than the doping concentration of a second conductivity type below the pair of floating regions.

Abstract: Provided is a power semiconductor device comprising a pair of gate electrodes respectively disposed in a first trench and a second trench spaced apart from each other in a substrate; a body region having a first conductivity type disposed between the first trench and the second trench; a pair of floating regions having a first conductivity type spaced apart from each other and surrounding a bottom surface and at least one side surface of the first trench and the second trench, respectively; and a drift region having a second conductivity type which extends from below the pair of floating regions through a region between the pair of floating regions to the body region, wherein, in the drift region, the doping concentration of a second conductivity type between the pair of floating regions is higher than the doping concentration of a second conductivity type below the pair of floating regions.

Abstract: The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate.

Abstract: Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.

Abstract: Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to be separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type