Abstract: The present invention pertains to a composition having a protective effect during islet transplantation, and more specifically, to a composition containing a compound of chemical formula 1 or a pharmaceutically acceptable salt thereof, and capable of providing a protective effect against oxidative stress, inflammation, etc. during islet transplantation.

Abstract: A resistive memory device includes a first electrode, a resistive oxidation structure and a second electrode. The resistive oxidation structure has sets of oxidation layers stacked on the first electrode. Each set is made up of a first metal oxide layer and a second metal oxide layer which is disposed on and is thinner than the first metal oxide layer. The first metal oxidation layer of the first one of the sets of oxidation layers contacts an upper surface of the first electrode. The second electrode is formed on the resistive oxidation structure. The resistance of the oxidation structure can be changed by an electric field.

Abstract: A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.

Abstract: A resistive memory device includes a first electrode, a resistive oxidation structure and a second electrode. The resistive oxidation structure has sets of oxidation layers stacked on the first electrode. Each set is made up of a first metal oxide layer and a second metal oxide layer which is disposed on and is thinner than the first metal oxide layer. The first metal oxidation layer of the first one of the sets of oxidation layers contacts an upper surface of the first electrode. The second electrode is formed on the resistive oxidation structure.

Abstract: A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.

Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Abstract: In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.

Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Abstract: A CMOS semiconductor device and a method of manufacturing the same in which the gate induced drain leakage (GIDL) effect is reduced. In the semiconductor device of this invention, high concentration source/drain regions of a PMOS transistor are formed away from the gate pattern sidewall spacers. This is accomplished by using as an implant mask a dielectric film formed on an entire surface of a semiconductor substrate, where the semiconductor substrate includes a PMOS transistor region in an n-well, a low concentration source/drain regions of a PMOS transistor formed by using a gate pattern as an implant mask, the PMOS transistor gate pattern sidewall spacers, and an NMOS transistor region in a p-well with the NMOS transistor having both a low concentration and a high concentration source/drain regions.

Abstract: Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

Abstract: A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

Abstract: A trench isolation method of a semiconductor integrated circuit is provided. In the trench isolation method, a mask pattern which defines a first opening and a second opening wider than the first opening is formed on a semiconductor substrate. A first spacer for filling the first opening and a second spacer are formed at the sidewalls of the second opening. A sacrificial material layer pattern having an etching rate substantially equal to that of the semiconductor substrate is formed in the second opening surrounded by the second spacer. The semiconductor substrate under the first and second spacers is exposed by selectively removing the first and second spacers. A deep trench region and a shallow trench region are formed in the exposed semiconductor substrate and under the sacrificial material layer, respectively, by etching the exposed semiconductor substrate and the sacrificial material layer pattern. An isolation layer filling the deep trench region and the shallow trench region is formed.

Abstract: In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.

Abstract: A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

Abstract: A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

Abstract: A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.

Abstract: A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

Abstract: A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a sidewall-insulating layer along the sidewall and bottom of the trench, and depositing a trench-insulating layer in the trench and over the semiconductor substrate. The sidewall-insulating layer is formed to have a lower etch rate than the trench-insulating layer. As a result of this difference in etch rates, the sidewall-insulating layer is not damaged too much during wet etching processes that take place during the later part of manufacture. This makes the interface between the substrate, sidewall-insulating layer, and gate oxide more reliable.

Abstract: A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.

Abstract: A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.