Patents by Inventor Han-Soo Joo
Han-Soo Joo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307069Abstract: According to an embodiment of the present disclosure, a memory device, a peripheral circuit configured to perform a program operation, including a plurality of program loops, and a control logic configured to, in some of the plurality of loops of the program operation, control the peripheral circuit to apply a program voltage to a selected word line, apply a first pass voltage to adjacent word lines that are adjacent to the selected word line, and then apply a second pass voltage to adjacent word lines at a predetermined time point, wherein the second pass voltage has a different magnitude compared to the first pass voltage, and in the rest of the plurality of loops of the program operation, control the peripheral circuit to apply the second pass voltage to the adjacent word lines at a time point that is different from the predetermined time point from a selected loop.Type: ApplicationFiled: June 6, 2022Publication date: September 28, 2023Applicant: SK hynix Inc.Inventor: Han Soo JOO
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Patent number: 11557355Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: GrantFiled: February 28, 2022Date of Patent: January 17, 2023Assignee: SK hynix Inc.Inventors: Sung Hoon Cho, Jae Sung Sim, Han Soo Joo, Hee Chang Chae, Se Kyoung Choi
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Publication number: 20220180951Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: SK hynix Inc.Inventors: Sung Hoon CHO, Jae Sung SIM, Han Soo JOO, Hee Chang CHAE, Se Kyoung CHOI
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Patent number: 11309029Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.Type: GrantFiled: September 21, 2020Date of Patent: April 19, 2022Assignee: SK hynix Inc.Inventors: Han Soo Joo, Bong Yeol Park, Ji Hyun Seo, Hee Youl Lee
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Patent number: 11302404Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: GrantFiled: July 8, 2020Date of Patent: April 12, 2022Assignee: SK hynix Inc.Inventors: Sung Hoon Cho, Jae Sung Sim, Han Soo Joo, Hee Chang Chae, Se Kyoung Choi
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Publication number: 20210241838Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.Type: ApplicationFiled: July 8, 2020Publication date: August 5, 2021Applicant: SK hynix Inc.Inventors: Sung Hoon CHO, Jae Sung SIM, Han Soo JOO, Hee Chang CHAE, Se Kyoung CHOI
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Publication number: 20210005260Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Inventors: Han Soo JOO, Bong Yeol PARK, Ji Hyun SEO, Hee Youl LEE
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Publication number: 20200395075Abstract: A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Applicant: SK hynix Inc.Inventors: Han Soo JOO, Ji Hyun SEO, Hee Youl LEE
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Patent number: 10854296Abstract: A semiconductor device includes strings each having a plurality of memory cells. The strings are coupled between a common source line and a bit line. A method of operating the semiconductor device includes applying a pre-program voltage to a selected word line coupled to a selected memory cell and to an unselected word line coupled to an unselected memory cell adjacent to the selected memory cell among the plurality of memory cells. The method further includes applying a first program voltage to the selected word line.Type: GrantFiled: July 3, 2019Date of Patent: December 1, 2020Assignee: SK hynix Inc.Inventors: Ji Hyun Seo, Bong Yeol Park, Hee Youl Lee, Han Soo Joo
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Patent number: 10811097Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.Type: GrantFiled: July 3, 2019Date of Patent: October 20, 2020Assignee: SK hynix Inc.Inventors: Han Soo Joo, Bong Yeol Park, Ji Hyun Seo, Hee Youl Lee
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Patent number: 10790024Abstract: A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.Type: GrantFiled: May 28, 2019Date of Patent: September 29, 2020Assignee: SK hynix Inc.Inventors: Han Soo Joo, Ji Hyun Seo, Hee Youl Lee
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Publication number: 20200202933Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.Type: ApplicationFiled: July 3, 2019Publication date: June 25, 2020Inventors: Han Soo JOO, Bong Yeol PARK, Ji Hyun SEO, Hee Youl LEE
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Publication number: 20200168280Abstract: A semiconductor device includes strings each having a plurality of memory cells. The strings are coupled between a common source line and a bit line. A method of operating the semiconductor device includes applying a pre-program voltage to a selected word line coupled to a selected memory cell and to an unselected word line coupled to an unselected memory cell adjacent to the selected memory cell among the plurality of memory cells. The method further includes applying a first program voltage to the selected word line.Type: ApplicationFiled: July 3, 2019Publication date: May 28, 2020Applicant: SK hynix Inc.Inventors: Ji Hyun SEO, Bong Yeol PARK, Hee Youl LEE, Han Soo JOO
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Publication number: 20200143883Abstract: A semiconductor device and method of operating a semiconductor device, the semiconductor device includes memory strings coupled between a common source line and a bit line, and a peripheral circuit coupled to the memory strings through a plurality of word lines and a dummy word line, and configured to set bias of the word lines and the dummy word line before performing a read operation, wherein the peripheral circuit applies a first pass voltage to the word lines concurrently with applying an initial voltage lower than the first pass voltage to the dummy word line, and increases the first pass voltage and the initial voltage to a second pass voltage to set the bias of the word lines and the dummy word line.Type: ApplicationFiled: May 28, 2019Publication date: May 7, 2020Applicant: SK hynix Inc.Inventors: Han Soo JOO, Ji Hyun SEO, Hee Youl LEE
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Patent number: 9849171Abstract: This invention provides kits, devices, and methods for the detection of antibodies that recognize one or more proteins and/or antigens from porcine reproductive and respiratory syndrome virus (PRRSV). The antibodies may be in a biological fluid of a PRRSV infected or at risk subject. The invention may be advantageously applied to both the diagnosis and prevention of PRRSV infection.Type: GrantFiled: June 14, 2016Date of Patent: December 26, 2017Assignee: Regents of the University of MinnesotaInventor: Han-Soo Joo
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Publication number: 20160287691Abstract: This invention provides kits, devices, and methods for the detection of antibodies that recognize one or more proteins and/or antigens from porcine reproductive and respiratory syndrome virus (PRRSV). The antibodies may be in a biological fluid of a PRRSV infected or at risk subject. The invention may be advantageously applied to both the diagnosis and prevention of PRRSV infection.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Applicant: Regents of the University of MinnesotaInventor: Han-Soo Joo
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Patent number: 9454999Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.Type: GrantFiled: November 25, 2014Date of Patent: September 27, 2016Assignee: SK hynix Inc.Inventor: Han Soo Joo
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Patent number: 9401370Abstract: A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate are disposed on sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.Type: GrantFiled: September 7, 2012Date of Patent: July 26, 2016Assignee: SK Hynix Inc.Inventors: Sang-Moo Choi, Byung-Soo Park, Sang-Hyun Oh, Han-Soo Joo
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Patent number: 9388218Abstract: This invention provides kits, devices, and methods for the detection of antibodies that recognize one or more proteins and/or antigens from porcine reproductive and respiratory syndrome virus (PRRSV). The antibodies may be in a biological fluid of a PRRSV infected or at risk subject. The invention may be advantageously applied to both the diagnosis and prevention of PRRSV infection.Type: GrantFiled: July 16, 2010Date of Patent: July 12, 2016Assignee: Regents of the University of MinnesotaInventor: Han-Soo Joo
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Publication number: 20150078107Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.Type: ApplicationFiled: November 25, 2014Publication date: March 19, 2015Inventor: Han Soo Joo