Abstract: A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.

Abstract: According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Abstract: A timing controller, a source driver, and a display driver integrated circuit (DDI) having improved test efficiency and a method of operating the DDI are provided. The timing controller includes a code generation unit for generating a first code from display data, a protocol encoder for generating a data sequence including the display data and the first code, and a transmission unit for providing the data sequence to a source driver through a link.

Abstract: A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Abstract: A display driver circuit includes a source driver and a display driver. The source driver drives source lines of a display panel, and the timing controller transmits image data to the source driver and controls the source driver such that the transmitted image data is displayed in the display panel. The timing controller randomizes the image data in a scrambling mode when the timing controller transmits data packets including pixel data field in which the image data is written.

Abstract: A method of transferring data between a timing controller and a plurality of source drivers in a display device is disclosed. The method includes: (a) setting a first source driver of the plurality of source drivers to convert first signals having first voltage levels to second signals having second voltage levels; (b) receiving, by the first source driver, a first test pattern from the timing controller; (c) performing a test by the first source driver, based on the first test pattern, to determine whether an error has occurred in the first test pattern; and (d) when an error has occurred in the first test pattern, adjusting, by the first source driver, an output level of a receiver of the first source driver, so that the first source driver converts the first signals to third signals having third voltage levels different from the second voltage levels.

Abstract: According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Abstract: A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

Abstract: An output of a driving circuit is controlled by selectively outputting a first voltage or a second voltage as an N-th output voltage level in response to a first control signal and an N-th input voltage level, where N is a natural number, and pre-charging the selected N-th output voltage level to a third voltage or a fourth voltage, in response to a second control signal, the pre-charging being preformed based on the selected N-th output voltage level and a newly input (N+1)th input voltage level.

Abstract: A voltage adder includes a first amplifier, a feedback resistor, and a control current source. The first amplifier includes a first input terminal to which a first voltage is input, a second input terminal connected to a feedback node, and an output terminal connected to an output node. The feedback resistor is connected between the output node and the feedback node. The control current source allows an addition current corresponding to a second voltage to flow through the feedback resistor.

Abstract: An output of a driving circuit is controlled by selectively outputting a first voltage or a second voltage as an N-th output voltage level in response to a first control signal and an N-th input voltage level, where N is a natural number, and pre-charging the selected N-th output voltage level to a third voltage or a fourth voltage, in response to a second control signal, the pre-charging being preformed based on the selected N-th output voltage level and a newly input (N+1)th input voltage level.

Abstract: An Organic Light Emitting Display (OLED) includes an array of OLED devices and an incremental OLED brightness compensation system/method. The incremental OLED brightness compensation system/method is configured to incrementally change an electrical supply of the array of OLED devices in response to monitoring a measure of variation between an actual brightness and a desired brightness of the array of OLED devices, so as to cause the OLED to incrementally attain the desired brightness.

Abstract: An active matrix organic electroluminescent display including a circuit to supply a zero data voltage, and a method of driving thereof. A driver of the organic electroluminescent display includes a zero data process block which outputs a zero data voltage enable signal when pixel data that is to be displayed is zero data, and a circuit to transmit zero data voltage corresponding to the zero data to a pixel in response to the zero data voltage enable signal. The organic electroluminescent display and the driver thereof separately include the circuit for supplying zero data voltage, and thus zero data can be accurately displayed.

Abstract: A current-driven data driver IC includes a bias voltage generator configured to generate a plurality of bias voltages, a decoder configured to select one of the plurality of bias voltages based on a video data signal, and a digital-to-analog converter configured to receive the selected bias voltage and to responsively generate an output current based on the video data signal. A display device includes a display panel including a plurality of scan lines, a plurality of data lines intersecting the scan lines, and a plurality of pixels connected to the scan lines and the data lines, a timing controller configured to receive a video signal and to output a video data signal for driving the display panel, a scan driver IC configured to sequentially activate the scan lines, and a current-driven data driver IC configured to provide a drive current for the display device.

Abstract: A display device having a data driver integrated circuit with an improved transistor matching characteristic and a method of driving the same are provided. The display device includes a pixel, a voltage generator generating and outputting a plurality of bias voltages, and a current source supplying a current to the pixel in response to one of the bias voltages corresponding to an image data signal.

Abstract: A driving circuit of an active matrix method in a display device is disclosed, which can compensate luminance deviation of the display device according to threshold voltage deviation of a driving unit. The driving circuit of the active matrix method includes a switching unit switching a current applied from the driving unit to the display device, and a deviation compensator detecting the current applied to the display device by switching of a second switch, and controlling a control voltage, thereby compensating luminance deviation of the display device according to threshold voltage deviation of the driving unit.

Abstract: A driving circuit of an active matrix method in a display device is disclosed, which can compensate luminance deviation of the display device according to threshold voltage deviation of a driving unit. The driving circuit of the active matrix method includes a switching unit switching a current applied from the driving unit to the display device, and a deviation compensator detecting the current applied to the display device by switching of a second switch, and controlling a control voltage, thereby compensating luminance deviation of the display device according to threshold voltage deviation of the driving unit.