Abstract: A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection.

Abstract: A flash memory using hot carrier injection and a method of operating the same are provided. A plurality of strings constituting a page are formed on a single p-well and share the p-well. During a program operation, a string selection transistor is turned off, and electrons are accumulated in a source or drain region in response to a bias voltage applied to the p-well. Thereafter, the accumulated electrons are trapped in a charge trap layer of a memory cell in response to a program voltage applied through a word line. Also, during an erase operation, holes accumulated in response to a bias voltage applied to the p-well are trapped in the charge trap layer in response to an erase voltage. The flash memory performs NAND-type program and erase operations using hot carrier injection.

Abstract: A method of fabricating a SOI substrate is disclosed, which includes the steps of: forming trenches in the Si substrate; forming an oxidation preventing film over the Si substrate and at the side-walls of the trenches; forming grooves at the bottoms of trenches by etching the Si substrate using the oxidation preventing film as a mask; carrying out an oxidation using to form an oxide film and a Si device layer isolated by the oxide film; removing the oxidation preventing film; and carrying out a planarization to form the silicon-on-insulator substrate having a planar surface.

Abstract: A method and apparatus for measuring the metallurgical channel length of a semiconductor device includes the steps of determining capacitance of gate to substrate in a multiple MOS transistor pattern and MOS capacitor pattern which have the same gate area; subtracting the capacitance of gate to substrate in a MOS transistor from that in a MOS capacitor for providing a difference curve; determining the overlap length by using the capacitance corresponding to a peak shown in the differences curve; and subtracting two times the overlap length .DELTA.L from the gate length Ldrawn in the MOS transistor for providing the metallurgical channel length.