Abstract: A single memory package includes: a substrate; and a memory chip and a buffer chip that are integrated over the substrate, wherein the memory chip includes an interface modulator embedded therein, and the interface modulator is a serializing modulator including a multi-level amplitude modulator.

Abstract: A semiconductor memory device includes a memory cell array, a storage circuit suitable for storing pattern data, a data input circuit suitable for receiving normal write data from an external device, a comparison circuit suitable for comparing the pattern data with the normal write data based on a pre-read control signal, and generating a comparison signal corresponding to the comparison result, and a write circuit suitable for writing the pattern data to the memory cell array based on a pre-write control signal, and writing some of the normal write data to the memory cell array based on a normal write control signal and the comparison signal.

Abstract: A semiconductor memory device includes a memory cell array, a storage circuit suitable for storing pattern data, a data input circuit suitable for receiving normal write data from an external device, a comparison circuit suitable for comparing the pattern data with the normal write data based on a pre-read control signal, and generating a comparison signal corresponding to the comparison result, and a write circuit suitable for writing the pattern data to the memory cell array based on a pre-write control signal, and writing some of the normal write data to the memory cell array based on a normal write control signal and the comparison signal.

Abstract: A semiconductor memory device having banks includes an address input path selection circuit in each of the banks, the address input path selection circuit including a signal input unit configured to selectively activate a Y-address input enable signal in response to a bank-specific read/write signal, and a latch unit configured to latch the Y-address input enable signal. The address input path selection circuit reduces circuit area by reducing delay elements and prevents malfunction by operating only in a bank active state.

Abstract: A voltage pumping device is provided which includes a source voltage generator for generating a source voltage which has a first voltage level for a predetermined period and a second voltage level after a lapse of the predetermined period, the second voltage level being constant, and a pumping circuit configured to receive the source voltage and pump a predetermined voltage.

Abstract: In the auto precharge circuit, a plurality of read auto precharge signal generating units and a plurality of auto precharge signal output units share a single write auto precharge signal generating unit. Each read auto precharge signal generating unit logically combines an internal CAS command signal, an internal address signal and a pre auto precharge signal to generate an auto precharge detect signal and a read auto precharge signal. The write auto precharge signal generating unit delays the read auto precharge signal by a predetermined time to generate a write auto precharge signal. Each auto precharge signal output unit logically combines the internal CAS command signal, an internal address signal, a read auto precharge signal, and a write auto precharge signal to output an auto precharge signal.

Abstract: A semiconductor memory device having banks includes an address input path selection circuit in each of the banks, the address input path selection circuit including a signal input unit configured to selectively activate a Y-address input enable signal in response to a bank-specific read/write signal, and a latch unit configured to latch the Y-address input enable signal. The address input path selection circuit reduces circuit area by reducing delay elements and prevents malfunction by operating only in a bank active state.

Abstract: In the auto precharge circuit, a plurality of read auto precharge signal generating units and a plurality of auto precharge signal output units share a single write auto precharge signal generating unit. Each read auto precharge signal generating unit logically combines an internal CAS command signal, an internal address signal and a pre auto precharge signal to generate an auto precharge detect signal and a read auto precharge signal. The write auto precharge signal generating unit delays the read auto precharge signal by a predetermined time to generate a write auto precharge signal. Each auto precharge signal output unit logically combines the internal CAS command signal, an internal address signal, a read auto precharge signal, and a write auto precharge signal to output an auto precharge signal.

Abstract: A voltage pumping device is provided which includes a source voltage generator for generating a source voltage which has a first voltage level for a predetermined period and a second voltage level after a lapse of the predetermined period, the second voltage level being constant, and a pumping circuit configured to receive the source voltage and pump a predetermined voltage.