Abstract: A tracer diffusion device includes: a first container, for holding a first fluid containing a tracer; a second container, for holding a second fluid; a drilling pipe; wherein, a first end of the drilling pipe is connected to the first container; a second end of the drilling pipe is extended into a borehole; and the second end of the drilling pipe is equipped with a first sealing capsule and a second sealing capsule; a plurality of through holes are arranged on the drilling pipe between the first sealing capsule and the second sealing capsule; a unidirectional driving device, arranged on the drilling pipe, for injecting the first fluid from the first container into the borehole between the first sealing capsule and the second sealing capsule; and a bidirectional driving device, arranged between the second container and the first sealing capsule.

Abstract: A discontinuous transmission (DTX) information transmission method is provided. The DTX information transmission method may include the following steps. A processor of an apparatus may determine whether to enter a DTX mode. A transceiver of the apparatus may transmit DTX information to a network node in response to determining to enter the DTX mode.

Abstract: A transaction record is created showing a purchase transaction of a customer. A CV profile showing a list of items in the transaction obtained from images is also obtained. The items in the transaction record are compared to items on the list. When there is a discrepancy, an action to take is determined.

Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.

Abstract: Disclosed is a screenshot method, applicable to an electronic device. The electronic device includes an input unit and a touch screen, and the touch screen is configured to display an image. The screenshot method includes: receiving a first screenshot signal using the input unit or the touch screen; taking a screenshot of the touch screen according to the first screenshot signal, and selectively enabling a successive screenshot function according to the first screenshot signal; and taking a screenshot of the touch screen according to a second screenshot signal when the successive screenshot function is enabled, where the second screenshot signal is different from the first screenshot signal. The disclosure further provides an electronic device and a computer program product.

Abstract: A compressor (200), comprising: a first rotor (20) being rotatable around a first axis (11), the first rotor (20) comprising a first portion (22) and a second portion (24); and a first shaft (10) carrying the first portion (22) and the second portion (24), the first shaft (10) having a first end (12) and a second end (14) that are oppositely arranged, wherein the first rotor (20) is configured to be applied with a preset acting force in a direction from the first end (12) toward the second end (14) or from the second end (14) toward the first end (12) during rotation. The size of the compressor (200) can be reduced with the displacement of the compressor (200) remaining substantially unchanged.

Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.

Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.

Abstract: The present disclosure provides antibodies and antibody fragments thereof that bind to human TNFR2. The disclosed antibodies, inhibit the TNF-TNFR2 signaling axis and enhance cytokine secretion in T effector cells and are therefore useful for the treatment of cancer, either alone or in combination with other agents.

Abstract: Disclosed herein are photoactivable fluorophores comprising one or more thiocarbonyl groups as well as conjugates and compositions thereof. The present disclosure also provides methods of preparing photoactivatable fluorophores as well as methods of imaging using the photoactivatable fluorophores, conjugates, and compositions of the present disclosure.

Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.

Abstract: A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.

Abstract: Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.

Abstract: A rotor assembly, a compressor and an air conditioner are provided. The rotor assembly includes a first rotation shaft and a first rotor rotatably arranged on the first rotation shaft. The first rotor includes a plurality of first screw blades, and a first tooth slot is formed between two adjacent first screw blades; a suction end of the first rotor has at least one oil slinger slot, to allow a lubricant to enter the first tooth slot through the at least one oil slinger slot. It is ensured that the lubricant can fully lubricate and seal the first tooth slot, so that the compressor can run more smoothly, reduce wear of screw blades and improve the service life of the compressor.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers, two epitaxial structures, a conductive structure, a via, and a graphene barrier. The channel layers and the epitaxial structures are disposed over the substrate. The channel layers are connected between the epitaxial structures. The conductive structure is disposed on the substrate opposite to the epitaxial structures. The via is connected between one of the epitaxial structure and the conductive structure. The graphene barrier surrounds the via.

Abstract: A scanner comprises a mirror, a first piezoelectric actuator, a second piezoelectric actuator, a third piezoelectric actuator, a fourth piezoelectric actuator, a first connecting member, a second connecting member, a first mirror spring, a second mirror spring, a stationary member, a first plurality of actuator springs, a second plurality of actuator springs, a third plurality of actuator springs, a fourth plurality of actuator springs, a first plurality of electrodes, and a second plurality of electrodes. The scanner is driven by piezoelectric actuators. A method of fabricating the scanner comprises the steps of providing a wafer; oxidation; deposition; patterning; and applying a singulation process.

Abstract: Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.

Abstract: The present invention discloses a camera optical lens including, from an object side to an image side in sequence: a first lens having a negative refractive power, a second lens having a negative refractive power, a third lens having a positive refractive power, a fourth lens having a negative refractive power, and a fifth lens having a positive refractive power. The camera optical lens satisfies the following conditions: 12.00?TTL/f?15.00, 2.00?f45/f?6.00, 0?(R3+R4)/(R3?R4)<1.00, and 8.00?d4/d6?30.00. The camera optical lens according to the present invention has excellent optical characteristics, such as large aperture, wide angle, and ultra-thin.

Abstract: A thermal immersion circulator comprising a housing defining a cavity, a heater comprising a heating element, wherein at least a portion of the heating element is located within the cavity of the housing, a coupling assembly securing the heater within the housing, and a seal isolating the coupling assembly from direct contact with the heater. The heater comprises a side surface having longitudinal axis, a fluid inlet in communication with a fluid outlet, and a fluid heating portion located between the fluid inlet and the fluid outlet. The heater also comprises at least one seal located adjacent the outlet and a heating element wrapped at least partially about the fluid heating portion.

Abstract: A semiconductor structure is disclosed. In one example, the semiconductor structure includes: a device region having at least one semiconductor device; a dummy region in contact with the device region; and at least one thermal conductor embedded in the dummy region.