Abstract: A motor includes a rotor and a stator. The rotor comprises a rotating shaft and an impeller. The impeller couples with the rotating shaft and has a hub. The hub has an outer surface, an inner surface, a plurality of first through holes and a plurality of second through holes. The first through holes are disposed nearer the rotating shaft than the second through holes. The stator comprises a silicon steel sheet and a bearing assembly. The silicon steel sheet has an annular portion and a plurality of protruding portions. The rotating shaft couples with the bearing assembly and penetrates within an inner hole of the annular portion. Each protruding portion is extended outward from the annular portion and has an extending length. The distance between the first through hole and the nearest second through hole is in a range of 0.3 to 1.2 times of the extending length.

Abstract: In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: A method for driving a cholesteric liquid crystal display, wherein the method includes steps as follows: Firstly, a reflective cholesteric liquid crystal panel including a pixel array composed of a plurality of pixel units is provided. Next, a scanning operation is performed on the pixel array. The scanning operation includes steps as follows: A continuous fixed pulse is applied to at least one of the plurality of pixel units lasting for a time period, so as to make a cholesterol liquid crystal layer of the at least one of the plurality of pixel units having a uniform lying helix (ULH) phase; and a maintaining pulse that is smaller than the continuous fixed pulse is applied to the at least one of the plurality of pixel units.

Abstract: An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.

Abstract: Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: A color correction method is applied to an image correction apparatus having an image sensor, and includes searching a color deviation area within a detection image, analyzing the detection image to estimate a correction color value of the color deviation area, and calibrating the color deviation area by the correction color value to generate a calibrated detection image without color deviation.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: A display apparatus and an image displaying method are provided. The display apparatus includes a display module and a driving circuit. The driving circuit is coupled to the display module and receives an input image. The driving circuit determines a watermark area and a non-watermark area of the display module according to watermark information, and at least one of the watermark area and the non-watermark area is alternately driven by a first gamma curve and a second gamma curve. A brightness difference percentage between the first gamma curve and the second gamma curve at a same grayscale value between 10% and 90% of a grayscale percentage is between 0.2 and 0.6.

Abstract: A motor includes a rotor and a stator. The rotor comprises a rotating shaft and an impeller. The impeller couples with the rotating shaft and has a hub. The hub has an outer surface, an inner surface, a plurality of first through holes and a plurality of second through holes. The first through holes are disposed nearer the rotating shaft than the second through holes. The stator comprises a silicon steel sheet and a bearing assembly. The silicon steel sheet has an annular portion and a plurality of protruding portions. The rotating shaft couples with the bearing assembly and penetrates within an inner hole of the annular portion. Each protruding portion is extended outward from the annular portion and has an extending length. The distance between the first through hole and the nearest second through hole is in a range of 0.3 to 1.2 times of the extending length.

Abstract: In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.

Abstract: A color correction method is applied to an image correction apparatus having an image sensor, and includes searching a color deviation area within a detection image, analyzing the detection image to estimate a correction color value of the color deviation area, and calibrating the color deviation area by the correction color value to generate a calibrated detection image without color deviation.

Abstract: A tangential flow filtration module includes plural plate units connected in sequence. Each of the plate units includes a main body, a first combing portion, a second combing portion, a first flange and a second flange. The main body has a first side surface, a second side surface and a through hole. The first side surface is opposite to the second side surface, and the through hole extends from the first side surface to the second side surface. The first combing portion and the second combing portion are disposed on the first side surface and the second side surface respectively. The first flange and the second flange respectively protrude from the first side surface and the second side surface and respectively. The first combing portion of one of the plate units is combined with the second combing portion of another one of the plate units, so that a sieving structure.

Abstract: An electrochemical detection system is configured to detect a sample. The electrochemical detection system includes an electrochemical test strip and a measuring instrument. The electrochemical test strip includes a main body and at least one electrode group. The measuring instrument is electrically connected to the at least one electrode group. The measuring instrument is adapted to determine whether a flow field condition of the sample is normal via the at least one electrode group.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.