Patents by Inventor Han-Ul Lee

Han-Ul Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140102766
    Abstract: Disclosed herein is a multi-layer type coreless substrate, including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated on one surface or both surfaces of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting a pillar disposed on an outermost insulating layer of the plurality of insulating layers.
    Type: Application
    Filed: March 14, 2013
    Publication date: April 17, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Da Hee Kim, Yoong Oh, Ki Young Yoo, Han Ul Lee, Myung Sam Kang, Ki Hwan Kim
  • Publication number: 20130146349
    Abstract: The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.
    Type: Application
    Filed: June 4, 2012
    Publication date: June 13, 2013
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventor: Han Ul Lee
  • Publication number: 20120168220
    Abstract: Disclosed herein are a multi-layer printed circuit board and a method of manufacturing the same. In the multi-layer printed circuit board and the method of manufacturing the same, circuit layers formed in a plurality of insulating layers are electrically interconnected through vias formed in a lump, thereby making it possible to secure bonding reliability of an interlayer circuit layer and more stably secure performance of the printed circuit board. In addition, since a stacked type via structure may be implemented by performing a via hole drilling process, a desmear process, and a copper plating process only one time after an insulating layer and an circuit layer are stacked, a manufacturing process, a manufacturing time, and manufacturing costs of the stacked type via structure may be reduced.
    Type: Application
    Filed: October 25, 2011
    Publication date: July 5, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Ul Lee, Byung Bae SEO, Chang Sup RYU, Yong Sam LEE
  • Publication number: 20100147575
    Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board can include: processing a first hole, which has a tapered shape, in one side of a substrate by using a laser drill; processing a second hole, which has a tapered shape and which connects with the first hole, in the other side of the substrate by using a laser drill in a position corresponding to that of the first hole; and forming a conductive portion, which electrically connects both sides of the substrate through the first hole and the second hole, by performing plating. This method may be used for providing reliable interlayer connections.
    Type: Application
    Filed: November 6, 2009
    Publication date: June 17, 2010
    Inventors: Han-Ul Lee, Young-Hwan Shin, Jong-Jin Lee
  • Patent number: 7050883
    Abstract: An off-line feed rate scheduling method of a CNC machining process includes selecting a constraint variable and inputting a reference value related to the constraint variable; estimating a cutting configuration where a maximum constraint variable value (CVV) occurs through ME Z-map modeling; receiving the estimated cutting configuration and estimating a specific rotation angle (?s) where the maximum constraint variable value occurs through constraint variable modeling; calculating a feed rate that satisfies the reference value of the constraint variable at the estimated specific rotation angle; and applying the calculated feed rate to the NC code. Cutting force or machined surface error may be selected as a constraint variable depending on machining conditions.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: May 23, 2006
    Assignee: POSTECH Foundation
    Inventors: Dong-Woo Cho, Jeong-Hoon Ko, Han-Ul Lee
  • Publication number: 20050113963
    Abstract: An off-line feed rate scheduling method of a CNC machining process includes selecting a constraint variable and inputting a reference value related to the constraint variable; estimating a cutting configuration where a maximum constraint variable value (CVV) occurs through ME Z-map modeling; receiving the estimated cutting configuration and estimating a specific rotation angle (?s) where the maximum constraint variable value occurs through constraint variable modeling; calculating a feed rate that satisfies the reference value of the constraint variable at the estimated specific rotation angle; and applying the calculated feed rate to the NC code. Cutting force or machined surface error may be selected as a constraint variable depending on machining conditions.
    Type: Application
    Filed: March 3, 2004
    Publication date: May 26, 2005
    Inventors: Dong-Woo Cho, Jeong-Hoon Ko, Han-Ul Lee