Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.

Abstract: A target object tracking method, a camera, and a computer-readable storage medium are provided. The camera includes a telephoto lens and a wide-angle lens. The camera captures a telephoto image by the telephoto lens, and captures a wide-angle image by the wide-angle lens. When a target object is detected in the wide-angle image, a first zoom magnification of the wide-angle image and a zoom magnification of switching lenses are obtained. The wide-angle image is digitally zoomed according to the first zoom magnification if the first zoom magnification is less than or equal to the zoom magnification of switching lenses. Otherwise, if the first zoom magnification is greater than the zoom magnification of switching lenses, the telephoto image is digitally zoomed to output a tracking image of the target object when the target object is detected in the telephoto image.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking 10 structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Abstract: A method for forming an interconnect structure is provided. The method includes the following operations. A contact is formed over a substrate. An interlayer dielectric (ILD) layer is formed over the contact and the substrate. An opening is formed in the ILD layer thereby exposing a portion of the contact. A densified dielectric layer is formed at an exposed surface of the ILD layer by the opening and an oxide layer over the portion of the contact by irradiating a microwave on the exposed surface of the ILD layer.

Abstract: An apparatus and a method for effectively exhausting evaporated material are provided. In an embodiment the apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate. The exhaust hood assembly includes a trench plate, a cover plate over the trench plate and a single exhaust pipe header over and attached to a single exhaust opening of the cover plate. During operation, the exhaust hood assembly reduces the amount of condensation and also collects any remaining condensation in order to help prevent condensation from impacting further manufacturing steps.

Abstract: A capacitive coupling package structure includes a plurality of first leads, a plurality of second leads, two first coupling plates, two second coupling plates, a first chip, a second chip, a first package member, and a second package member. The two first coupling plates and the two second coupling plates are vertically separate from each other and are partially and vertically overlapped with each other, respectively.

Abstract: A method includes displaying a first virtual tribe in a virtual scene, the first virtual tribe is a virtual tribe with one or more first virtual objects of a first identity type in the virtual scene. The method includes displaying social interaction options for an acquisition of one or more skills across different virtual tribe. The social interaction options include identification information of a second virtual tribe, and candidate skill options for a second set of skills associated with the second virtual. The method further includes receiving a selection operation on a first skill option among the candidate skill options. The first skill option corresponds to a first skill in the second set of skills associated with the second virtual tribe. The selection operation on the first skill option indicates a triggering of an acquisition of the first skill corresponding to the first skill option.

Abstract: A method for forming a semiconductor device. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming an enhancement layer on each of the fins, such that the enhancement layer encapsulates each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the enhancement layer. The method also includes depositing an STI material on the fins and the device isolation structures, followed by recessing the fins relative to the STI material.

Abstract: An expandable home structure can expand outward from at least one side thereof to expand the living space once the home is delivered to a desired location. The expansion process includes raising two roof panels from a side edge of its main structure, where the roof panels follow a track so that an outer one of the two roof panels can, once fully raised, slide outward along front and rear walls of the expansion section so that the roof panels form a box gable roof structure over the expansion section.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer on the substrate; isolation structures extending through the dielectric layer into the substrate; and a floating gate on the dielectric layer and between the isolation structures, wherein the floating gate includes a first portion directly on the dielectric layer; and second portions on the sidewalls of the first portion.

Abstract: A data processing system includes: a processor; a memory storing executable instructions which, when executed by the processor, cause the processor, alone or in combination with other processors, to implement a client application with a user interface. The client application is configured to: receive an image depicting an object; generate a fine-tuning input to an image-generating Artificial Intelligence (AI) model to associate image data of the object with an identifier; with the fine-tuning input, fine-tune the AI model; structure a prompt for the AI model using the identifier; and obtain from the AI model a new customized image that depicts the object while preserving an appearance of the object.

Abstract: An optical engine module including a display panel, a transflective layer, a polarizing reflective layer, a first bifocal lens, a first and second electrically controlled half waveplate is provided. The transflective layer is disposed between the display panel and the polarizing reflective layer. The polarizing reflective layer is configured to allow the light beam having a first polarization state to pass through, and reflect the light beam having a second polarization state. The first and second electrically controlled half waveplate are disposed between the transflective layer and the polarizing reflective layer. The first bifocal lens disposed between the first and second electrically controlled half waveplate has a first focal length for the light beam with the first polarization state, and has a second focal length for the light beam with the second polarization state.

Abstract: The present invention pertains to methods of coating antimicrobial peptides on the biomaterial and the biomaterial coated thereby. The coating solution described herein comprises one or more antimicrobial peptides (AMPs) dissolved in a buffer containing an anionic surfactant, wherein the AMPs are amphipathic and cationic.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: A solid electrolyte three-electrode electrochemical test device comprises a housing, a working electrode, a counter electrode, a reference electrode, a first conductive structure, a second conductive structure, a third conductive structure, and a solid electrolyte layer. The housing comprises a groove and a first through hole located at a bottom of the groove. The reference electrode is insulated from the counter electrode. The first conductive structure and the working electrode are stacked with each other, and the working electrode and at least a part of the first conductive structure are located in the first through hole. The solid electrolyte layer, the counter electrode, the reference electrode, the second conductive structure and the third conductive structure are located in the groove, and the first conductive structure, the working electrode, the solid electrolyte layer, the counter electrode, and the second conductive structure are sequentially stacked and located coaxially with each other.

Abstract: Parallel processing of inter prediction of a current coding block and preceding coding blocks depending on the partition depth of the current coding block is disclosed. An apparatus comprises a processing circuitry configured for: obtaining a value of a parameter for the current coding block, wherein the value of the parameter indicates a partition depth of the current coding block, and performing an inter prediction process for the current coding block; wherein no Motion Vector Predictor candidate comprising a motion vector of a coded block of the picture that is not spatially adjacent to the current coding block for the current coding block is used in the inter prediction process or a merge mode inter prediction process comprised in the inter prediction process, when the value of the parameter for the current coding block is greater than a threshold.

Abstract: Devices and methods for Intra prediction are provided. The method includes: obtaining a value of an indication information of a current block. When the value of the indication information indicates the intra prediction mode of the current block is not comprised in the set of most probable modes, deriving the intra prediction mode IntraPredModeY of the current block by the following ordered steps: i. IntraPredModeY is set equal to intra_luma_mpm_remainder[xCb][yCb], ii. The value of IntraPredModeY is incremented by one. The method can improve the efficiency to determine the intra prediction mode of the current block.