Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: A control system includes a locomotion device that is configured to accompany a moving object such as a human operator or a robotic device. The control system is configured to control a motion of the locomotion device based on a location of at least one of the moving object relative to the locomotion device or a location of the locomotion device relative to the moving object. The control system is configured to control the locomotion device to maintain a position of the locomotion device with respect to the moving object to thereby synchronize the motion of the locomotion device with a motion of the moving object.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: A control system includes a locomotion device that is configured to accompany a moving object such as a human operator or a robotic device. The control system is configured to control a motion of the locomotion device based on a location of at least one of the moving object relative to the locomotion device or a location of the locomotion device relative to the moving object. The control system is configured to control the locomotion device to maintain a position of the locomotion device with respect to the moving object to thereby synchronize the motion of the locomotion device with a motion of the moving object.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: An azimuth thruster system includes a pod configured to rotate relative the hull of the ship about an azimuthal axis of the pod, a propeller shaft extending from the pod and being configured to rotate relative to the pod about a central axis of the propeller shaft, an outer shaft disposed at least partially in the pod and configured to be driven by a first primary prime mover, an inner shaft disposed at least partially within the outer shaft and configured to be driven by a second primary prime mover, and a pod gear unit disposed within the pod and coupled to the outer shaft, the inner shaft, and the propeller shaft. The outer and inner shafts are configured to rotate at least one of the pod and the propeller shaft based on directions and magnitudes of the torques generated by the first and second primary prime movers.

Abstract: An azimuth thruster system includes a pod configured to rotate relative the hull of the ship about an azimuthal axis of the pod, a propeller shaft extending from the pod and being configured to rotate relative to the pod about a central axis of the propeller shaft, an outer shaft disposed at least partially in the pod and configured to be driven by a first primary prime mover, an inner shaft disposed at least partially within the outer shaft and configured to be driven by a second primary prime mover, and a pod gear unit disposed within the pod and coupled to the outer shaft, the inner shaft, and the propeller shaft. The outer and inner shafts are configured to rotate at least one of the pod and the propeller shaft based on directions and magnitudes of the torques generated by the first and second primary prime movers.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

Abstract: A system for operating a horizontal axis wind turbine includes a turbine rotor and a rotor blade adapted to rotate about a horizontal axis, two vertical shafts, a plurality of gears adapted to translate a rotational motion of the turbine rotor into counter-rotating vertical rotational motions of the shafts, and two generators fixed to a tower, adapted to translate a rotational motion of the shafts into electrical power. A method of operating a horizontal axis wind turbine system includes obtaining a turbine rotor and a rotor blade adapted to rotate about a horizontal axis, obtaining two vertical shafts, obtaining a plurality of gears, and obtaining two generators fixed to a tower, translating a rotational motion of the turbine rotor into counter-rotating vertical rotational motions of the shafts using the gears, and translating a rotational motion of the shafts into electrical power using the generators.

Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.

Abstract: Systems and methods for operating horizontal axis wind turbine systems are disclosed. A system includes a turbine rotor and a rotor blade adapted to rotate about a horizontal axis, two vertical shafts, a plurality of gears adapted to translate a rotational motion of the turbine rotor into counter-rotating vertical rotational motions of the shafts, and two generators fixed to a tower, adapted to translate a rotational motion of the shafts into electrical power. A method of operating a horizontal axis wind turbine system includes obtaining a turbine rotor and a rotor blade adapted to rotate about a horizontal axis, obtaining two vertical shafts, obtaining a plurality of gears, and obtaining two generators fixed to a tower, translating a rotational motion of the turbine rotor into counter-rotating vertical rotational motions of the shafts using the gears, and translating a rotational motion of the shafts into electrical power using the generators.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.

Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

Abstract: An integrated circuit. The integrated circuit includes a plurality of functional units, wherein each of the plurality of functional units is implemented on a die of the integrated circuit. Each of the functional units includes one or more temperature sensors. The integrated circuit further includes a temperature control unit coupled to each of the functional units, wherein the temperature control unit is configured to monitor a temperature of each of the plurality of functional units based on temperature information provided from the temperature sensors. The temperature control unit is configured to, if the temperature exceeds a first threshold value for a particular one of the plurality of functional units, perform a first temperature control action on the particular one of the plurality of functional units independently of other ones of the plurality of functional units.

Abstract: Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.