Patents by Inventor Han Wu

Han Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153492
    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing error corrections for memory systems are provided. In one aspect, a memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to: read data from a data page of the memory, perform a first phase Error-Correcting Code (ECC) test on the read data based on first ECC data associated with the data, and in response to determining that the read data fails to pass the first phase ECC test, perform a second phase ECC test on a portion of the read data based on second ECC data. The first ECC data is stored together with the data in the data page. The second ECC data is associated with a portion of the data corresponding to the portion of the read data, and stored in a redundancy page different from the data page.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: November 26, 2024
    Assignee: Macronix International Co., Ltd.
    Inventors: Sheng-Han Wu, Yu-Ming Huang
  • Patent number: 12151136
    Abstract: An exercise device may include a base frame and an interface frame. An exercise device may include a support beam hingedly coupled to the base frame and hingedly coupled to the interface frame. A device may include a first strut hingedly coupled to the support beam and the interface frame, such that the first strut comprises an adjustable length configured to adjust at least one of: a height of the interface frame with respect to the base frame, or an orientation of the interface frame with respect to the base frame. An exercise device may include a second strut hingedly coupled to the support beam and the base frame, such that the second strut comprises an adjustable length configured to adjust at least one of: a height of the interface frame with respect to the base frame, or an orientation of the interface frame with respect to the base frame.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: November 26, 2024
    Assignee: Freak Athlete Essentials LLC
    Inventors: Yogesh Taxak, Benjamin Alfred Elster, Liang Han Wu
  • Patent number: 12155464
    Abstract: A communication method includes receiving, by a terminal device, first clock source information. The first clock source information corresponds to clock source information of a wireless communication system. The first clock source information indicates that a fifth generation (5G) system clock is useable as a clock source. The method further includes sending, by the terminal device, the first clock source information to an adjacent device.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: November 26, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hancheng Li, Han Zhou, Wenfu Wu
  • Patent number: 12153433
    Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Kang Hu, Cheng-Hung Chen, Yan-Han Chen, Feng-Kuang Wu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 12150427
    Abstract: An intelligent defecation device for living creature includes a device body, a supporting portion, an image module, and a first analysis module. The supporting portion is formed within the inner side of the device body for accommodating a moisture absorption member so as to allow the living creature to leave over its excrement therein. The image module is also arranged at the device body for dynamically capturing the images of the excrement in the supporting portion and outputting the image. The first analysis module is arranged in the device body and connected with the image module to analyze and calculate the defecation mode with the image based on preset or accumulated data, so as to generate a signal when an abnormal defecation mode is diagnosed.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: November 26, 2024
    Assignee: LuluPet Co., Ltd.
    Inventors: James Cheng-Han Wu, Pei-Hsuan Shih, Chun-Ming Su, You-Gang Kuo, Ning-Yuan Lyu, Chi-Yeh Hsu, Liang-Hao Huang
  • Publication number: 20240389213
    Abstract: A dispensing system includes a dispense material supply that contains a dispense material and a dispensing pump connected downstream from the dispense material supply. The dispensing pump includes a body made of a first electrically conductive material, one or more first electrical contacts that are disposed on the body of the dispensing pump, and one or more first connection wires that are coupled between each one of the one or more first electrical contacts and ground. The dispensing system also includes a dispensing nozzle connected downstream from the dispensing pump and includes a tube made of a second electrically conductive material, one or more second electrical contacts that are disposed on an outer surface of the tube, and one or more second connection wires that are coupled between each one of the one or more second electrical contacts and the ground.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yang LIN, Yu-Cheng CHANG, Cheng-Han WU, Shang-Sheng LI, Chen-Yu LIU, Chen Yi HSU
  • Publication number: 20240387352
    Abstract: A capacitive coupling package structure includes a plurality of first leads, a plurality of second leads, two first coupling plates, two second coupling plates, a first chip, a second chip, a first package member, and a second package member. The two first coupling plates and the two second coupling plates are vertically separate from each other and are partially and vertically overlapped with each other, respectively.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 21, 2024
    Inventors: YOU-FA WANG, TING-WEI KAO, CHIA-YUN LEE, YUAN-LUNG WU, PU-HAN LIN
  • Publication number: 20240387272
    Abstract: A method for forming a semiconductor device. The method includes performing a first etching process to define one or more fins and corresponding device isolation structures on a substrate. The method further includes forming an enhancement layer on each of the fins, such that the enhancement layer encapsulates each fin. The method further performs a second etching process to remove one or more of the fins, and performs a third etching process to remove a portion of the enhancement layer. The method also includes depositing an STI material on the fins and the device isolation structures, followed by recessing the fins relative to the STI material.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Inventors: Zhen-Nong Wu, Mao-Chia Wang, Jia-Ren Chen, Li-Yi Chen, Wen Han Hung, Che-Li Lin, Yen-Ning Chen
  • Publication number: 20240385463
    Abstract: An optical engine module including a display panel, a transflective layer, a polarizing reflective layer, a first bifocal lens, a first and second electrically controlled half waveplate is provided. The transflective layer is disposed between the display panel and the polarizing reflective layer. The polarizing reflective layer is configured to allow the light beam having a first polarization state to pass through, and reflect the light beam having a second polarization state. The first and second electrically controlled half waveplate are disposed between the transflective layer and the polarizing reflective layer. The first bifocal lens disposed between the first and second electrically controlled half waveplate has a first focal length for the light beam with the first polarization state, and has a second focal length for the light beam with the second polarization state.
    Type: Application
    Filed: May 15, 2024
    Publication date: November 21, 2024
    Applicant: Coretronic Corporation
    Inventors: Tzu-Hung Lin, Chung-Yang Fang, Wen-Chun Wang, Ching-Chuan Wei, Bo-Han Cheng, Wei-Ting Wu
  • Publication number: 20240387521
    Abstract: A semiconductor device includes a substrate including a well region of a first conductive type; a first gate electrode on the substrate; a second gate electrode on the substrate; a first doped region embedded within the well region and is of the first conductive type, a second doped region embedded within the well region and is of the first conductive type, and a third doped region embedded within the well region and is of the first conductive type; and a first interconnection structure electrically connecting the first gate electrode and the second gate electrode. The first doped region and the second doped region are on opposite sides of the first gate electrode.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Ho-Hsiang CHEN, Chi-Hsien LIN, Ying-Ta LU, Hsien-Yuan LIAO, Hsiu-Wen WU, Chiao-Han LEE, Tzu-Jin YEH
  • Publication number: 20240387546
    Abstract: A semiconductor structure includes a first transistor and a second transistor. The first transistor includes a first fin structure and a first metal gate over the first fin structure. The first metal gate includes a first work function metal layer and a first gap-filling metal layer. The second transistor includes a second fin structure and a second metal gate over the second fin structure. The second metal gate includes a second work function metal layer and a second gap-filling metal layer. The first metal gate and the second metal gate provide a same work function. A width of the first metal gate is equal to a width of the second metal gate. A width of a top surface of the first gap-filling metal layer is greater than a width of a top surface of the second gap-filling metal layer.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: PO-YING CHANG, WEN-LANG WU, CHANG-TAI LEE, LI-CHUNG KUO, YUN-HAN LIN, CHEN-CHUAN YANG
  • Publication number: 20240388717
    Abstract: A video encoding apparatus includes a content activity analyzer circuit and a video encoder circuit. The content activity analyzer circuit applies a content activity analysis process to a plurality of frames, and generate a plurality of content activity analysis results, wherein the plurality of frames are derived from a plurality of input frames of the video encoding apparatus. The video encoder circuit performs a video encoding process to generate a bitstream output of the video encoding apparatus. At least one frame is not encoded into the bitstream output according to the plurality of content activity analysis results.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chin-Jung Yang, Chun-Kai Huang, Ping-Han Lee, Tzu-Yun Tseng, Tung-Hsing Wu
  • Patent number: 12149169
    Abstract: A power converter having a multi-slope compensation mechanism is provided. A multi-slope compensation circuit of the power converter includes a plurality of first capacitors, a comparator and a plurality of first resistors. A first terminal of each of the plurality of first capacitors and a node between a second terminal of a high-side switch and a first terminal of a low-side switch are connected to an inductor. A plurality of first input terminals of a comparator are respectively connected to second terminals of the plurality of first capacitors, and are respectively connected to first terminals of the plurality of first resistors. Second terminals of the plurality of first resistors are coupled to a second reference voltage. A second input terminal of the comparator is coupled to a first reference voltage. An output terminal of the comparator is connected to an input terminal of a driver circuit.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: November 19, 2024
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Cheng-Han Wu, Fu-Chuan Chen
  • Publication number: 20240379437
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Publication number: 20240379448
    Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Hsin-Han Tsai, Chung-Chiang Wu, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Publication number: 20240379826
    Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20240374944
    Abstract: A battery module capable of suppressing spread of battery fire including a case, a plurality of battery packs, a plurality of temperature sensors, an energy consumption module and a controller. The case forms an accommodation space, and the battery packs is accommodated in the accommodation space. The temperature sensors are dispersedly configured to the accommodation space, and the temperature sensors respectively detect an ambient temperature around configure locations. The controller is coupled to the temperature sensors, and when the ambient temperature detected by one of the temperature sensors is greater than or equal to a first specific temperature range, the controller controls the energy consumption module to consume a battery capacity of at least one battery pack around the one of the temperature sensors.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventors: Chung-Hsing CHANG, Wen-Yi CHEN, Way-Lung WU, Teng-Chi HUANG, Shi-Cheng TONG, Yong-Han CHEN, Yu-Chun WANG
  • Publication number: 20240377826
    Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Kang HU, Cheng-Hung CHEN, Yan-Han CHEN, Feng-Kuang WU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
  • Publication number: 20240378234
    Abstract: The present teaching relates to a method, system, and programming for searching content. A sketch of an object is obtained from a user. The sketch is processed by a neural network to generate an image corresponding to the sketch of the object. One or more features are extracted from the image, and one or more images previously stored are identified that have features similar to the one or more features. The one or more images are provided to the user.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei-Lun Su, Wen-Hsuan Wu, Ching-Han Chang, Tzu-Chiang Liou
  • Publication number: 20240379565
    Abstract: Embodiments include a method for forming an integrated circuit package. A first dielectric layer is deposited over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer. A first metallization pattern is formed extending along and through the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region. The second dielectric layer is removed from the scribe line region, the second dielectric layer remaining in the package region. After the second dielectric layer is removed from the scribe line region, a second metallization pattern is formed extending along and through the second dielectric layer. The wafer and the first dielectric layer are sawed in the scribe line region.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 14, 2024
    Inventors: Wei-An Tsao, Chen Yu Wu, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo