Patents by Inventor Hana Chockler
Hana Chockler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230281460Abstract: A data processing apparatus comprises at least one processor configured to execute an input module to receive an input dataset comprising a plurality of samples, each assigned to one of a plurality of variables, an encoder module to map the input dataset to a latent representation, a decoder module to process the latent representation and indicate a link category for each pair of variables, wherein the link category is selected from a set of categories including ‘no causal link’, ‘causally linked’ and ‘unknown’, and a reinforcement learning, RL, module to: (i) compare the link category for each pair of variables with the samples for the associated variables, (ii) generate a score function including an error term based on a result of the comparison, and (iii) update one or more parameters of the encoder module and decoder module based on the score function.Type: ApplicationFiled: February 17, 2023Publication date: September 7, 2023Inventors: Hana Chockler, Daniel McNamee, Andrew Lawrence, Steven Kleinegesse, Maksim Sipos
-
Patent number: 9389984Abstract: A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify portions of the computer program that correspond to one or more bug patterns; and performing verification of the computer program, wherein the verification comprises traversing a control flow graph of the computer program and tracking symbolic values of variables of the computer program, wherein said performing comprises directing the traversal of the control flow graph to nodes of the control flow graph that correspond to the identified portions, whereby bug-prone portions of the computer program are prioritized to be verified before non-bug-prone portions of the computer program.Type: GrantFiled: September 10, 2013Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Hana Chockler, Oded Margalit, Dmitry Pidan, Sitvanit Ruah
-
Patent number: 8996339Abstract: Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.Type: GrantFiled: September 7, 2011Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Hana Chockler, Alexander Ivrii, Arie Matsliah, Shiri Moran, Ziv Nevo
-
Publication number: 20150074652Abstract: A method, apparatus, and product for avoiding similar counter-examples in model checking. One method comprises model checking of a program by traversing control flow paths of the program to determine states associated with execution of the program, each state comprises at least symbolic values of variables; said traversing is biased to give preference to traversing control flow paths that are substantially different than control flow paths associated with traces of the program; whereby said model checking is guided away from executions that are similar to the traces. A second method comprises obtaining a counter-example produced by a model checker, computing a distance between a control flow path of the counter-example and between a set of one or more control flow paths of additional counter-examples; and in response to the distance being below a threshold, dropping the counter-example.Type: ApplicationFiled: September 10, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: HANA CHOCKLER, ODED MARGALIT, DMITRY PIDAN, SITVANIT RUAH
-
Publication number: 20150074651Abstract: A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify portions of the computer program that correspond to one or more bug patterns; and performing verification of the computer program, wherein the verification comprises traversing a control flow graph of the computer program and tracking symbolic values of variables of the computer program, wherein said performing comprises directing the traversal of the control flow graph to nodes of the control flow graph that correspond to the identified portions, whereby bug-prone portions of the computer program are prioritized to be verified before non-bug-prone portions of the computer program.Type: ApplicationFiled: September 10, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: HANA CHOCKLER, ODED MARGALIT, DMITRY PIDAN, SITVANIT RUAH
-
Patent number: 8903700Abstract: An abstract trace may be defined based on a coverage goal. An execution of a System Under Test (SUT) is guided in accordance with the coverage goal. Non-deterministic decision, which correlates to receiving a stimulus to the SUT, is decided based on a probability function. After one or more executions, the probability function is modified based on a measurement of similarity between the abstract trace and each of the one or more executions. The modification of the probability function may be performed using on Cross-Entropy method. The modification is performed in order to cause determination of non-deterministic decisions in executions to better correlate with the abstract trace. In some exemplary embodiments, a determination whether the abstract trace is reachable is determined based on a rate of convergence of the executions to the abstract trace.Type: GrantFiled: May 24, 2010Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Hana Chockler, Sharon Keidar-Barner
-
Patent number: 8856755Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.Type: GrantFiled: January 27, 2013Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Hana Chockler, Dmitry Pidan, Sitvanit Ruah, Karen Yorav
-
Publication number: 20140215445Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.Type: ApplicationFiled: January 27, 2013Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Hana Chockler, Dmitry Pidan, Sitvanit Ruah, Karen Yorav
-
Publication number: 20140208297Abstract: A computer implemented method, an computerized apparatus and a computer program product for validating revised computer programs. The method performed by a computerized device, comprising: validating a computer program having one or more revised instructions, wherein said validating comprises: checking the computer program with respect to only a portion of a Control Flow Graph (CFG) of the computer program, wherein the portion of the CFG including all paths of the CFG that include at least one node associated with a revised instruction.Type: ApplicationFiled: January 20, 2013Publication date: July 24, 2014Applicant: International Business Machines CorporationInventors: Hana Chockler, Sitvanit Ruah
-
Patent number: 8639490Abstract: A trace associated with an abstraction of a target device is utilized to guide an execution of the target device to be substantially similar to the trace. An execution of the target device determines a non-deterministic decision based on a probability function. The probability function is configured to increase the likelihood that the execution will be substantially similar to the abstracted trace. Cross-entropy method may be utilized to guide the execution of the target device.Type: GrantFiled: March 8, 2010Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Hana Chockler, Sharon Keidar-Barner
-
Patent number: 8448147Abstract: A coverage analysis tool may determine coverage in respect to heterogeneous coverage tasks associated with different hierarchy levels of a tasks hierarchy. The coverage analysis tool may iteratively refine coverage tasks to determine coverage of sub-tasks. In some cases, coverage tasks may be unrefined in order to reduce overhead of coverage analysis in performance of the software under test, such that the software under test may perform in an essentially similar manner as in non-testing mode.Type: GrantFiled: February 15, 2010Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Orna Raz, Eitan Farchi, Yochai Ben-Chaim, Hana Chockler, Lawrence Blount, Aviad Zlotnick
-
Publication number: 20130060545Abstract: Method, apparatus, and product for performing incremental formal verification. A computer-implemented method performed by a computerized device. The method comprises: obtaining invariants with respect to a first model; determining a portion of the invariants that are invariants with respect to a second model, and utilizing the portion of the invariants to check that the second model holds a property.Type: ApplicationFiled: September 7, 2011Publication date: March 7, 2013Applicant: International Business Machines CorporationInventors: Hana Chockler, Alexander Ivrii, Arie Matsliah, Shiri Moran, Ziv Nevo
-
Patent number: 8327334Abstract: A method for replay of program executions using cross-entropy is provided. The method comprises identifying a first sequence of decision points, wherein the first sequence represents a first execution of a logic code; identifying a second sequence of decision points, wherein the second sequence represents a second execution of the logic code; computing a distance between the first and second executions; and minimizing the distance between the first and second executions using cross-entropy, in response to determining that the second execution is not within a predetermined threshold distance of the first execution.Type: GrantFiled: April 9, 2008Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Hana Chockler, Eitan Daniel Farchi, Benyamin Godlin
-
Patent number: 8056059Abstract: A method for detecting the occurrence of rare events in an executable logic code includes assigning a first probability of a chance of traversal of one or more decision paths, in which each path connects two decision points defined by execution of the logic code. As a result of execution of the logic code, the decision paths traversed are evaluated to determine whether said traversal conforms to a predefined performance function. The performance function defines a goal to be achieved pursuant to the execution of the logic code. A second probability is assigned to the chance of traversal of at least one of said one or more decision paths to increase the likelihood that the one or more decision paths are traversed in a subsequent execution of the logic code in a closer conformity with the predefined performance function.Type: GrantFiled: October 17, 2007Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Hana Chockler, Eitan Daniel Farchi, Benyamin Godlin, Sergey Novikov
-
Publication number: 20110218793Abstract: A trace associated with an abstraction of a target device is utilized to guide an execution of the target device to be substantially similar to the trace. An execution of the target device determines a non-deterministic decision based on a probability function. The probability function is configured to increase the likelihood that the execution will be substantially similar to the abstracted trace. Cross-entropy method may be utilized to guide the execution of the target device.Type: ApplicationFiled: March 8, 2010Publication date: September 8, 2011Applicant: International Business Machines CorporationInventors: Hana Chockler, Sharon Keidar-Barner
-
Publication number: 20110218794Abstract: An abstract trace may be defined based on a coverage goal. An execution of a System Under Test (SUT) is guided in accordance with the coverage goal. Non-deterministic decision, which correlates to receiving a stimulus to the SUT, is decided based on a probability function. After one or more executions, the probability function is modified based on a measurement of similarity between the abstract trace and each of the one or more executions. The modification of the probability function may be performed using on Cross-Entropy method. The modification is performed in order to cause determination of non-deterministic decisions in executions to better correlate with the abstract trace. In some exemplary embodiments, a determination whether the abstract trace is reachable is determined based on a rate of convergence of the executions to the abstract trace.Type: ApplicationFiled: May 24, 2010Publication date: September 8, 2011Applicant: International Business Machines CorporationInventors: Hana Chockler, Sharon Keidar-Barner
-
Publication number: 20110202904Abstract: A coverage analysis tool may determine coverage in respect to heterogeneous coverage tasks associated with different hierarchy levels of a tasks hierarchy. The coverage analysis tool may iteratively refine coverage tasks to determine coverage of sub-tasks. In some cases, coverage tasks may be unrefined in order to reduce overhead of coverage analysis in performance of the software under test, such that the software under test may perform in an essentially similar manner as in non-testing mode.Type: ApplicationFiled: February 15, 2010Publication date: August 18, 2011Applicant: International Business Machiness CorporationInventors: Orna Raz, Eitan Farchi, Yochai Ben-Chaim, Hana Chockler, Lawrence Blount, Aviad Zlotnick
-
Patent number: 7921411Abstract: A method for verifying software program code includes specifying a property that the software program code is expected to satisfy. The software program code and the property are transformed into an initial logical formula in a static single assignment (SSA) form, the formula including variables. A loop in the software program code is identified. Successive over-approximations are applied to a portion of the initial logical formula corresponding to the loop in order to produce a modified logical formula in the SSA form that represents a finite over-approximation of a set of states that are reachable by the loop. It is verified that the software program code satisfies the specified property by determining whether there is an assignment of the variables that satisfies the modified logical formula.Type: GrantFiled: October 20, 2006Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Hana Chockler, Ziv Glazberg, Benyamin Godlin, Sharon Keidar-Barner
-
Patent number: 7853932Abstract: System, method and computer program product for checking a software entity, the method includes: providing a direct acyclic graph representative of possible execution paths of the software entity; wherein multiple successor nodes that succeed a certain parent node are associated with different execution probabilities; randomly selecting a successor node out of the multiple successor nodes in response the execution probabilities; and checking the software entity in response to the selection.Type: GrantFiled: July 10, 2006Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Hana Chockler, Eitan Daniel Farchi, Ziv Glazberg, Benyamin Godlin
-
Publication number: 20100131930Abstract: Reporting on software test coverage, where a set of coverage tasks and a coverage task hierarchy have been established for a software under test (SUT). Establishing a coverage task subset, the subset including at least one coverage task hierarchy element at a level above the lowest coverage task hierarchy level. Identifying when, during a software test, a coverage task in the coverage task subset was completed. Outputting to a user the identity of those portions of the coverage task that have been completed. Refining the coverage task subset in one of the following fashions through the coverage task hierarchy in accordance with user input: depth first progression, breadth first progression.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: International Business Machines CorporationInventors: Yochai Ben-Chaim, Lawrence Carter Blount, Hana Chockler, Eitan Farchi, Orna Raz-Pelleg, Aviad Zlotnick