Patents by Inventor Hanae Ikeda

Hanae Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9288040
    Abstract: According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N?1.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Endo, Yuichi Komano, Koichi Fujisaki, Hideo Shimizu, Hanae Ikeda, Atsushi Shimbo
  • Patent number: 9166789
    Abstract: According to an embodiment, a cryptographic processing apparatus performs processes to encrypt plain text or decrypt cipher text. The processes include a non-linear process using multiplication. The non-linear process is a process performed using intermediate data masked with mask data. The intermediate data is data in a middle of the plurality of processes. The mask data hides the intermediate data. The apparatus includes a non-linear processing unit configured to receive first data that is an exclusive OR of a product of the intermediate data and first mask data and second mask data, and output second data that is an exclusive OR of a product of data obtained by the non-linear process on the intermediate data and data obtained by the non-linear process on the first mask data and third mask data having a predetermined correspondence relation with the second mask data.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hanae Ikeda, Takeshi Kawabata
  • Patent number: 8924448
    Abstract: An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taichi Isogai, Kenichiro Furuta, Hirofumi Muratani, Kenji Ohkuma, Tomoko Yonemura, Yoshikazu Hanatani, Atsushi Shimbo, Hanae Ikeda, Yuichi Komano
  • Patent number: 8828900
    Abstract: The exhaust gas purification catalyst according to the present invention has a substrate 54, a lower layer 57 disposed on this substrate 54, and an upper layer 58 disposed on this lower layer 57. The upper layer 58 is provided with a first catalyst and a second catalyst, and the lower layer 57 is provided with a first catalyst. This first catalyst has Al2O3 as a carrier and Pt and Pd as noble metals supported on the Al2O3, while the second catalyst typically has an Al2O3—ZrO2—TiO2 complex oxide as a carrier and has Pd as a noble metal supported on the Al2O3—ZrO2—TiO2 complex oxide. Moreover, the upper layer 58 has a hydrocarbon adsorbent 68.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 9, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Nobuyuki Takagi, Yuichi Sobue, Hanae Ikeda, Masaya Kamada, Ryoichi Inde
  • Patent number: 8782114
    Abstract: According to one embodiment, a representation converting unit converts a set of n elements (h0, h1, . . . , hn?1) (hi: a member of a finite field Fp^m, 0?i?n?1) that is a projective representation of a member g of an n-th degree algebraic torus Tn(Fp^m) (n: positive integer, p: prime number, m: positive integer) into a limited projected representation expressed by a set of n elements (h?0, h?1, . . . , h?n?1) (h?i: a member of the finite field Fp^m, 0?i?n?1) in which at least one element out of the n elements is a zero element 0 or an identity element 1. An arithmetic unit omits part of Fp^m operation that is arithmetic operation in the finite field Fp^m based on a fact that an element in the set of n elements (h?0, h?1, . . . , h?n?1) represented by the limited projective representation is a zero element “0” or an identity element “1” when performing Fp^mn operation that is arithmetic operation of a finite field Fp^mn in combination with the Fp^m operation.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Taichi Isogai, Hirofumi Muratani, Atsushi Shimbo, Yoshikazu Hanatani, Kenichiro Furuta, Kenji Ohkuma, Yuichi Komano, Hanae Ikeda
  • Publication number: 20140057776
    Abstract: The exhaust gas purification catalyst according to the present invention has a substrate 54, a lower layer 57 disposed on this substrate 54, and an upper layer 58 disposed on this lower layer 57. The upper layer 58 is provided with a first catalyst and a second catalyst, and the lower layer 57 is provided with a first catalyst. This first catalyst has Al2O3 as a carrier and Pt and Pd as noble metals supported on the Al2O3, while the second catalyst typically has an Al2O3—ZrO2—TiO2 complex oxide as a carrier and has Pd as a noble metal supported on the Al2O3—ZrO2—TiO2 complex oxide. Moreover, the upper layer 58 has a hydrocarbon adsorbent 68.
    Type: Application
    Filed: April 6, 2012
    Publication date: February 27, 2014
    Inventors: Nobuyuki Takagi, Yuichi Sobue, Hanae Ikeda, Masaya Kamada, Ryoichi Inde
  • Publication number: 20140030158
    Abstract: The oxidation catalyst for exhaust gas purification provided by the present invention includes a support supporting a noble metal that catalyzes the oxidation of carbon monoxide (CO). The support is mainly constituted by a composite metal oxide including, in terms of oxides, Al and Zr, or Al, Zr and Ti at the following mass ratios: Al2O3 40 to 99% by mass, ZrO2 1 to 45% by mass, and TiO2 0 to 15% by mass.
    Type: Application
    Filed: April 6, 2012
    Publication date: January 30, 2014
    Inventors: Nobuyuki Takagi, Yuichi Sobue, Hanae Ikeda, Masaya Kamada, Ryoichi Inde
  • Patent number: 8538017
    Abstract: According to one embodiment, in an encryption device, a segmentation unit segments masked plain data into pieces of first segmented data. A first processing unit generates pieces of second segmented data from the pieces of first segmented data. A nonlinear transform unit generates pieces of third segmented data transformed from the pieces of second segmented data. A data integration unit integrates fourth segmented data to generate masked encrypted data. An unmask processing unit generates encrypted data from the masked encrypted data. The exclusive OR of the pieces of second segmented data matches the exclusive OR of input data, subjected to nonlinear transform processing and calculated from the plain data, and the first mask. The exclusive OR of the pieces of third segmented data matches the exclusive OR of transform data, obtained when the nonlinear transform processing is performed on the input data, and the second mask.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Endo, Hideo Shimizu, Yuichi Komano, Hanae Ikeda, Atsushi Shimbo
  • Publication number: 20130236005
    Abstract: According to an embodiment, a cryptographic processing apparatus performs processes to encrypt plain text or decrypt cipher text. The processes include a non-linear process using multiplication. The non-linear process is a process performed using intermediate data masked with mask data. The intermediate data is data in a middle of the plurality of processes. The mask data hides the intermediate data. The apparatus includes a non-linear processing unit configured to receive first data that is an exclusive OR of a product of the intermediate data and first mask data and second mask data, and output second data that is an exclusive OR of a product of data obtained by the non-linear process on the intermediate data and data obtained by the non-linear process on the first mask data and third mask data having a predetermined correspondence relation with the second mask data.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hanae Ikeda, Takeshi Kawabata
  • Patent number: 8533243
    Abstract: When converting an affine representation representing a 2r-th degree algebraic torus T2r(Fq) (r is a prime number, and q is an integer) to a projective representation representing a quadratic algebraic torus T2(Fq^r), a representation converting apparatus acquires member (c0, c1, . . . , cr-2), (ci is a member of a finite field Fq, where 0?i?r?2) of a 2r-th degree algebraic torus T2r(Fq) represented by the affine representation. The apparatus performs a multiplication operation on the acquired member. The multiplication operation is determined by a condition under which a member of a quadratic algebraic torus T2(Fq^r) is included in the 2r-th degree algebraic torus T2r(Fq), a modulus and a base of a quadratic extension, and a modulus and a base of an r-th degree extension. The representation converting apparatus then performs an addition and subtraction operation determined by the condition, the moduli, and the bases.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Hirofumi Muratani, Kenji Ohkuma, Hanae Ikeda, Taichi Isogai, Kenichiro Furuta, Yoshikazu Hanatani
  • Publication number: 20120307997
    Abstract: According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N?1.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 6, 2012
    Inventors: Tsukasa Endo, Yuichi Komano, Koichi Fujisaki, Hideo Shimizu, Hanae Ikeda, Atsushi Shimbo
  • Publication number: 20120295787
    Abstract: An exhaust gas purifying catalyst includes a catalyst powder that includes a ceria-zirconia composite oxide on which platinum (Pt) is supported, and a Ce/alumina powder that includes alumina which contains cerium (Ce) in the structure thereof. The Ce/alumina undergoes only a slight decrease in specific surface area even in a lean atmosphere at a high temperature. The Pt supported on the ceria-zirconia composite oxide forms a Pt—O—Ce bond with the Ce present on surfaces of Ce/alumina so that migration of Pt is restrained and sintering of Pt is prevented.
    Type: Application
    Filed: January 18, 2011
    Publication date: November 22, 2012
    Inventors: Hanae Ikeda, Takaaki Kanazawa
  • Publication number: 20120239721
    Abstract: An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taichi ISOGAI, Kenichiro Furuta, Hirofumi Muratani, Kenji Ohkuma, Tomoko Yonemura, Yoshikazu Hanatani, Atsushi Shimbo, Hanae Ikeda, Yuichi Komano
  • Patent number: 8233616
    Abstract: An encryption processing unit executes an arithmetic operation decided in advance and outputs an arithmetic result as an element on an algebraic torus. A compressing unit outputs, when the arithmetic result is an exceptional point representing an element on the algebraic torus that cannot be compressed by a compression map for compressing an element on the algebraic torus into affine representation, a compression result obtained by compressing the arithmetic result according to the compression map and outputs, when the arithmetic result is the exceptional point, an element belonging to a specific set decided in advance that does not overlap a set to which a compression result obtained by compressing the arithmetic result, which is not the exceptional point, belongs.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Muratani, Tomoko Yonemura, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani, Hanae Ikeda
  • Publication number: 20120124114
    Abstract: According to one embodiment, a representation converting unit converts a set of n elements (h0, h1, . . . , hn?1) (hi: a member of a finite field Fp?m, 0?i?n?1) that is a projective representation of a member g of an n-th degree algebraic torus Tn(Fp?m) (n: positive integer, p: prime number, m: positive integer) into a limited projected representation expressed by a set of n elements (h?0, h?1, . . . , h?n?1) (h?i: a member of the finite field Fp?m, 0?i?n?1) in which at least one element out of the n elements is a zero element 0 or an identity element 1. An arithmetic unit omits part of Fp?m operation that is arithmetic operation in the finite field Fp?m based on a fact that an element in the set of n elements (h?0, h?1, . . . , h?n?1) represented by the limited projective representation is a zero element “0” or an identity element “1” when performing Fp?mn operation that is arithmetic operation of a finite field Fp?mn in combination with the Fp?m operation.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 17, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko YONEMURA, Taichi ISOGAI, Hirofumi MURATANI, Atsushi SHIMBO, Yoshikazu HANATANI, Kenichiro FURUTA, Kenji OHKUMA, Yuichi KOMANO, Hanae IKEDA
  • Publication number: 20120069998
    Abstract: According to one embodiment, in an encryption device, a segmentation unit segments masked plain data into pieces of first segmented data. A first processing unit generates pieces of second segmented data from the pieces of first segmented data. A nonlinear transform unit generates pieces of third segmented data transformed from the pieces of second segmented data. A data integration unit integrates fourth segmented data to generate masked encrypted data. An unmask processing unit generates encrypted data from the masked encrypted data. The exclusive OR of the pieces of second segmented data matches the exclusive OR of input data, subjected to nonlinear transform processing and calculated from the plain data, and the first mask. The exclusive OR of the pieces of third segmented data matches the exclusive OR of transform data, obtained when the nonlinear transform processing is performed on the input data, and the second mask.
    Type: Application
    Filed: July 27, 2011
    Publication date: March 22, 2012
    Inventors: Tsukasa ENDO, Hideo Shimizu, Yuichi Komano, Hanae Ikeda, Atsushi Shimbo
  • Publication number: 20100049777
    Abstract: When converting an affine representation representing a 2r-th degree algebraic torus T2r(Fq) (r is a prime number, and q is an integer) to a projective representation representing a quadratic algebraic torus T2(Fq?r), a representation converting apparatus acquires member (c0,c1, . . . ,cr?2), (ci is a member of a finite field Fq, where 0?i?r?2) of a 2r-th degree algebraic torus T2r(Fq) represented by the affine representation. The apparatus performs a multiplication operation on the acquired member. The multiplication operation is determined by a condition under which a member of a quadratic algebraic torus T2(Fq?r) is included in the 2r-th degree algebraic torus T2r(Fq), a modulus and a base of a quadratic extension, and a modulus and a base of an r-th degree extension. The representation converting apparatus then performs an addition and subtraction operation determined by the condition, the moduli, and the bases.
    Type: Application
    Filed: March 4, 2009
    Publication date: February 25, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Yonemura, Hirofumi Muratani, Kenji Ohkuma, Hanae Ikeda, Taichi Isogai, Kenichiro Furuta, Yoshikazu Hanatani
  • Publication number: 20100046742
    Abstract: An encryption processing unit executes an arithmetic operation decided in advance and outputs an arithmetic result as an element on an algebraic torus. A compressing unit outputs, when the arithmetic result is an exceptional point representing an element on the algebraic torus that cannot be compressed by a compression map for compressing an element on the algebraic torus into affine representation, a compression result obtained by compressing the arithmetic result according to the compression map and outputs, when the arithmetic result is the exceptional point, an element belonging to a specific set decided in advance that does not overlap a set to which a compression result obtained by compressing the arithmetic result, which is not the exceptional point, belongs.
    Type: Application
    Filed: March 18, 2009
    Publication date: February 25, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirofumi MURATANI, Tomoko Yonemura, Atsushi Shimbo, Kenji Ohkuma, Taichi Isogai, Yuichi Komano, Kenichiro Furuta, Yoshikazu Hanatani, Hanae Ikeda
  • Patent number: 7266577
    Abstract: A modular multiplication apparatus comprises a calculation unit which comprises processing units including a multiplier-adder unit and performs a modular multiplication by carrying out pipeline processes by the processing units; and a calculator configured to, before a first pipeline process, carry out a predetermined calculation for a processing result of one of the processing units in a pipeline process immediately before the first pipeline process, and when the first pipeline processes supply a calculation result of the predetermined calculation to a processing unit at an initial stage of the first pipeline process.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hanae Ikeda, Kenji Kojima, Shinichi Kawamura
  • Patent number: 7159115
    Abstract: An encryption apparatus provided with a Feistel type encryption algorithm includes a function operation unit that operates a non-linear function, and changing unit configured to supply the function operation unit with random data unrelated to an encryption operation result. In this way, a countermeasure can be taken against a DPA attack following the end of an operation by the encryption operation apparatus provided with the Feistel type encryption algorithm.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: January 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Fujisaki, Atsushi Shimbo, Masahiko Motoyama, Hanae Ikeda, Yuuki Tomoeda