Abstract: A memory storage device includes: a memory controller configured to receive data from an outer device, and a nonvolatile memory connected to the memory controller, wherein the memory controller includes: a first buffer memory configured to store the data; a second buffer memory different from the first buffer memory; and a memory interface configured to provide the data provided from the first buffer memory to the nonvolatile memory, wherein the nonvolatile memory is configured to store the data, and provide a write done signal to the memory interface after storing the data, and wherein the memory controller is configured to copy the data stored in the first buffer memory to the second buffer memory in response to the write done signal, and remove the data stored in the first buffer memory after copying the data stored in the first buffer memory to the second buffer memory.

Abstract: A data processing system includes a host capable of pipelining execution of a command set including a plurality of commands by storing the commands in a buffer, and a data storage device including a NVMe controller that receives the commands and controls execution of data access operations corresponding to the respective commands, generates a completion response upon successfully executing each one of the commands, and stores the resulting completion responses in a buffer, wherein the NVMe controller extracts at least two of the completion responses stored in the buffer to generate a completion packet and transmits the completion packet to the host during a single transaction.

Abstract: A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error.

Abstract: A data processing system includes a host capable of pipelining execution of a command set including a plurality of commands by storing the commands in a buffer, and a data storage device including a NVMe controller that receives the commands and controls execution of data access operations corresponding to the respective commands, generates a completion response upon successfully executing each one of the commands, and stores the resulting completion responses in a buffer, wherein the NVMe controller extracts at least two of the completion responses stored in the buffer to generate a completion packet and transmits the completion packet to the host during a single transaction.

Abstract: A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error.

Abstract: A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.