Patents by Inventor Hanfang Pan
Hanfang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10638346Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity.Type: GrantFiled: August 11, 2016Date of Patent: April 28, 2020Assignee: QUALCOMM IncorporatedInventors: Parvathanathan Subrahmanya, Qiang Shen, Aamod Dinkar Khandekar, Mariam Motamed, Wanshi Chen, Hanfang Pan, Deepak Mathew
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Publication number: 20170094545Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity.Type: ApplicationFiled: August 11, 2016Publication date: March 30, 2017Inventors: Parvathanathan Subrahmanya, Qiang Shen, Aamod Dinkar Khandekar, Mariam Motamed, Wanshi Chen, Hanfang Pan, Deepak Mathew
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Patent number: 8798214Abstract: Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s).Type: GrantFiled: November 14, 2007Date of Patent: August 5, 2014Assignee: Qualcomm IncorporatedInventors: Michael Alexander Howard, June Namgoong, Hanfang Pan
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Patent number: 8614977Abstract: A wireless communication signal in Long Term Evolution (LTE) may be interleaved in a manner which permits a partitioning of a received inter-column bit-reversed interleaved code block for improved de-interleaving. The code block may be divided into equal subportions which may be simultaneously de-interleaved both forward and backward, and in parallel with other subportions. An even number of subportions may be provided. Dividing a received code block in this manner may improve de-interleaving performance.Type: GrantFiled: May 9, 2011Date of Patent: December 24, 2013Assignee: QUALCOMM IncorporatedInventors: Wenqing Wu, Hanfang Pan, Michael A. Howard
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Patent number: 8397123Abstract: Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.Type: GrantFiled: September 30, 2009Date of Patent: March 12, 2013Assignee: QUALCOMM IncorporatedInventors: Hanfang Pan, Michael A. Howard, Yongbin Wei, Michael A. Kongelf
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Patent number: 8374072Abstract: Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden.Type: GrantFiled: April 7, 2010Date of Patent: February 12, 2013Assignee: QUALCOMM IncorporatedInventors: Peter Gaal, Robert J. Fuchs, Yongbin Wei, Ke Liu, Hanfang Pan, Durga Prasad Malladi, Daniel T. Macek
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Patent number: 8255759Abstract: Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention.Type: GrantFiled: October 29, 2009Date of Patent: August 28, 2012Assignee: QUALCOMM IncorporatedInventors: Hanfang Pan, Yongbin Wei
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Publication number: 20110280133Abstract: Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded.Type: ApplicationFiled: May 10, 2011Publication date: November 17, 2011Applicant: QUALCOMM INCORPORATEDInventors: Wei-Hsin Chang, Hanfang Pan, Michael Alexander Howard, Wenqing Wu
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Publication number: 20110280185Abstract: A wireless communication signal in Long Term Evolution (LTE) may be interleaved in a manner which permits a partitioning of a received inter-column bit-reversed interleaved code block for improved de-interleaving. The code block may be divided into equal subportions which may be simultaneously de-interleaved both forward and backward, and in parallel with other subportions. An even number of subportions may be provided. Dividing a received code block in this manner may improve de-interleaving performance.Type: ApplicationFiled: May 9, 2011Publication date: November 17, 2011Applicant: QUALCOMM INCORPORATEDInventors: Wenqing Wu, Hanfang Pan, Michael Alexander Howard
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Publication number: 20110249548Abstract: Efficient apparatus and method for Zadoff-Chu (“Chu”) sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden.Type: ApplicationFiled: April 7, 2010Publication date: October 13, 2011Applicant: QUALCOMM INCORPORATEDInventors: Peter Gaal, Robert J. Fuchs, Yongbin Wei, Ke Liu, Hanfang Pan, Durga Prasad Malladi, Daniel T. Macek
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Publication number: 20110194430Abstract: Certain aspects of the disclosure propose a unified channel estimation algorithm that combines two or more channel estimation algorithms in a single piece of hardware or software. The proposed unified channel estimation may dynamically switch, based on one or more metrics, between different modes of operation that utilize different channel estimation algorithms.Type: ApplicationFiled: December 15, 2010Publication date: August 11, 2011Applicant: QUALCOMM INCORPORATEDInventors: Taesang Yoo, Tao Luo, Yongbin Wei, Hanfang Pan, Michael A. Howard
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Publication number: 20110143672Abstract: Certain aspects of the disclosure propose parallel channel estimation and interference cancellation in a wireless communications system. For each common reference signal tone offset, interference cancellation and channel estimation may be performed independently. The proposed channel estimation method may increase performance of a system.Type: ApplicationFiled: December 13, 2010Publication date: June 16, 2011Applicant: QUALCOMM INCORPORATEDInventors: Taesang Yoo, Tao Luo, Yongbin Wei, Hanfang Pan, Michael A. Howard
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Patent number: 7954016Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.Type: GrantFiled: March 4, 2010Date of Patent: May 31, 2011Assignee: Qualcomm IncorporatedInventors: Hanfang Pan, Inyup Kang, James Krysl
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Publication number: 20110107019Abstract: Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention.Type: ApplicationFiled: October 29, 2009Publication date: May 5, 2011Applicant: QUALCOMM INCORPORATEDInventors: Hanfang Pan, Yongbin Wei
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Publication number: 20110075615Abstract: Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicant: QUALCOMM INCORPORATEDInventors: Hanfang Pan, Michael A. Howard, Yongbin Wei, Michael A. Kongelf
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Publication number: 20100183096Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.Type: ApplicationFiled: March 4, 2010Publication date: July 22, 2010Applicant: QUALCOMM IncorporatedInventors: Hanfang Pan, Inyup Kang, James Krysl
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Patent number: 7729322Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.Type: GrantFiled: February 28, 2002Date of Patent: June 1, 2010Assignee: QUALCOMM IncorporatedInventors: Nischal Abrol, Jian Lin, Hanfang Pan, Simon Turner
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Patent number: 7702968Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.Type: GrantFiled: February 27, 2004Date of Patent: April 20, 2010Assignee: Qualcomm IncorporatedInventors: Hanfang Pan, Inyup Kang, James Krysl
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Patent number: 7606266Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.Type: GrantFiled: May 10, 2006Date of Patent: October 20, 2009Assignee: QUALCOMM IncorporatedInventors: Nischal Abrol, Jian Lin, Hanfang Pan, Simon Turner
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Publication number: 20090124204Abstract: Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s).Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Applicant: QUALCOMM INCORPORATEDInventors: Michael Alexander Howard, June Namgoong, Hanfang Pan